A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

A spread-spectrum-signal reception apparatus includes a controller to obtain a phase comparison value that is a phase of a spread code at a time at which initialization of a phase of the spread code is performed and which corresponds to a timing of a top of a frame of a received signal, and to output an initialization instruction including the phase comparison value when having determined that a current time is within a range of a time window; and a signal processor to demodulate the received signal in accordance with the spread code, to perform a frame synchronizing process on the demodulated signal to detect a frame timing, and to perform the initialization at a timing determined in accordance with a result of comparison between the phase comparison value included in the initialization instruction and a phase of the spread code at the frame timing.

In some examples, a circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the PFD.

A time synchronization method and apparatus includes determining a time difference between reference time and system time of an artificial intelligence device, where the reference time is timed by an internal clock of the artificial intelligence device and is aligned based on a satellite timing signal, or the reference time is timed by an internal clock of the artificial intelligence device; and adjusting the system time based on a preset step value if the time difference is greater than a preset value.

A method between a geolocation receiver and an identified transmitting satellite, the receiver being able to receive a composite radio signal including a plurality of navigation signals each transmitted by a transmitting satellite that is part of a satellite constellation, a method for validating the synchronization between a geolocation receiver and a transmitting satellite during a phase for acquiring an augmentation signal including geolocation correction and integrity data; the methods include, for each identified transmitting satellite, extracting received ephemeris words or received words of any type of the received signal associated with the identified satellite as it is received, and comparing at least one received word with at least one word of the same rank or stored for the identified satellite and/or for at least one other satellite; the validation or non-validation of the synchronization with the identified transmitting satellite depends on a predetermined false alarm probability and/or non-detection probability.

A method for communication includes obtaining a timing signal from a timing synchronization reference source, computing a system frame number (SFN)direct frame number (DFN) offset, creating a timing fingerprint using the timing signal and the SFN-DFN offset, the timing fingerprint also comprising additional timing information, entering the timing fingerprint into a database, continually updating the timing fingerprint, determining whether the timing signal remains within a threshold, if the timing signal exceeds the threshold, iterating the timing fingerprint, verifying the timing fingerprint to determine whether there is a timing inconsistency between a most recent timing fingerprint and current time, if the timing fingerprint is verified, using the SFN-DFN offset to derive current DFN timing to decode a sidelink control information (SCI) communication, and if the SCI communication is decoded, using the timing signal for communicating over a sidelink communication channel.

A candidate arbitrary-phase spread spectrum modulation technique that offers similar performance to spread continuous phase modulation (CPM) waveforms and additional capabilities for programming a chosen frequency domain spectra into the resulting spread spectrum signal. The proposed chaotic-FSK waveform is derived from high-order sequence-based spread spectrum signals, with multi-bit resolution chaos-based sequences defining incremental phase words, enabling real-time efficient generation of practically non-repeating waveforms. A result of the C-FSK formulation is a parameterized hybrid modulation capable of acting like a traditional sequence-based spread spectrum signal or a traditional frequency shift keying signal depending on chosen parameters. As such, adaptation in this modulation may be easily implemented as a time-varying evolution, increasing the security of the waveform while retaining many efficiently implementable receiver design characteristics of traditional PSK modulations.

An aspect of the present disclosure includes methods, systems, and computer-readable media for receiving a first timing reference signal and a second timing reference signal at a local device, wherein the second timing reference signal includes an internal timing reference, receiving a timing indication from a remote device, calculating a timing offset from at least one of a propagation delay, the timing indication, or the first timing reference signal, adjusting the internal timing reference based on the timing offset, and transmitting a message based on the internal timing reference.

An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.

A method for communication includes obtaining a timing signal from a timing synchronization reference source, computing a system frame number (SFN)-direct frame number (DFN) offset, creating a timing fingerprint using the timing signal and the SFN-DFN offset, the timing fingerprint also comprising additional timing information, entering the timing fingerprint into a database, continually updating the timing fingerprint, determining whether the timing signal remains within a threshold, if the timing signal exceeds the threshold, iterating the timing fingerprint, verifying the timing fingerprint to determine whether there is a timing inconsistency between a most recent timing fingerprint and current time, if the timing fingerprint is verified, using the SFN-DFN offset to derive current DFN timing to decode a sidelink control information (SCI) communication, and if the SCI communication is decoded, using the timing signal for communicating over a sidelink communication channel.