An embodiment of the disclosed MIMO transceiver uses a single master clock to generate (i) the sampling-clock signals for the analog-to-digital and digital-to-analog converters and (ii) the multiple electrical local-oscillator signals that are used in various channels of the transceiver's analog down- and up-converters to translate signals between the corresponding intermediate-frequency and RF bands. The MIMO transceiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signals and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. In embodiments designed for operating in the mmW band, the MIMO transceiver may also employ a frequency multiplier configured to multiply the master-clock frequency to generate an additional local-oscillator signal for translating signals between the mmW and RF bands.

An embodiment of the disclosed MIMO transceiver uses a single master clock to generate (i) the sampling-clock signals for the analog-to-digital and digital-to-analog converters and (ii) the multiple electrical local-oscillator signals that are used in various channels of the transceiver's analog down- and up-converters to translate signals between the corresponding intermediate-frequency and RF bands. The MIMO transceiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signals and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. In embodiments designed for operating in the mmW band, the MIMO transceiver may also employ a frequency multiplier configured to multiply the master-clock frequency to generate an additional local-oscillator signal for translating signals between the mmW and RF bands.

A signal interface unit for a distributed antenna system includes a channelized radio carrier interface configured to communicate an uplink channelized radio carrier for a radio frequency carrier to a channelized radio carrier base station interface; an antenna side interface configured to receive an uplink digitized radio frequency signal from the distributed antenna system communicatively coupled to the antenna side interface; and a signal conversion module communicatively coupled between the channelized radio carrier interface and the antenna side interface and configured to convert between the uplink digitized radio frequency signal and the uplink channelized radio carrier at least in part by adjusting at least one uplink attribute of the uplink digitized radio frequency signal received from the distributed antenna system to comply with requirements of the channelized radio carrier base station interface.

A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.

A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.

A computing device (such as a computer gaming console) uses only a single radio to concurrently communicate with a wireless network access point and wireless client devices such as game controllers or peripherals. To establish and maintain both a high-throughput link with the access point, and a low-latency link with the client device(s), the single Wi-Fi radio of the computing device is configured to periodically switch between a channel used for the high-throughput link and a different channel that is used for the low-latency link—thus implementing a combination of frequency division multiplexing (FDM) and time division multiplexing (TDM). The console may use aspects of the Wi-Fi protocol standard to ensure that periodically switching its single radio between the two channels is accomplished while maintaining reliable communication on both channels.

A computing device (such as a computer gaming console) uses only a single radio to concurrently communicate with a wireless network access point and wireless client devices such as game controllers or peripherals. To establish and maintain both a high-throughput link with the access point, and a low-latency link with the client device(s), the single Wi-Fi radio of the computing device is configured to periodically switch between a channel used for the high-throughput link and a different channel that is used for the low-latency link—thus implementing a combination of frequency division multiplexing (FDM) and time division multiplexing (TDM). The console may use aspects of the Wi-Fi protocol standard to ensure that periodically switching its single radio between the two channels is accomplished while maintaining reliable communication on both channels.

A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.

A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.

A communication system includes a repetitive orthogonal frequency-division multiplexing (“ROFDM”)transmitter communicating with an ROFDM receiver. The ROFDM transmitter includes an ROFDM modulator, which includes a K-point Fast Fourier Transform receiving a block of time-domain data symbols and generating an initial orthogonal frequency-division multiplexing symbol. The initial orthogonal frequency-division multiplexing symbol is based on a block of frequency-domain data symbols corresponding to the block of time-domain data symbols. The initial orthogonal frequency-division multiplexing symbol includes an ending part. The ROFDM modulator includes an orthogonal frequency-division multiplexing symbol repeater generating a repetitive orthogonal frequency-division multiplexing symbol by repeatedly reproducing the initial orthogonal frequency-division multiplexing symbol. The modulator includes a cyclic prefix adder pretending a cyclic prefix to the repetitive orthogonal frequency-division multiplexing symbol to generate a baseband transmitted signal. The cyclic prefix includes the ending part of the initial orthogonal frequency-division multiplexing symbol. The ROFDM receiver includes an ROFDM demodulator.