A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.

A method is provided. The method, comprises: power amplifying, with at least two parallel power amplifiers, at least two pre-distorted signals each corresponding to a unique transmit band, wherein each power amplifier operates in a unique transmit band; and pre-distorting, with a single pre-distortion system, at least two signals in different transmit bands, where the pre-distortion of each of the at least two signals is based upon a portion of a corresponding power amplified, pre-distorted signal, and where the pre-distortion diminishes certain IMD products in the corresponding power amplified, pre-distorted signal.

A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

The invention provides a method and apparatus that addresses and resolves the issues currently affecting the ability to offer Enhanced TV, in particular, those issues concerning timing and synchronization, interaction with other modules in the STB, and distribution.

According to one embodiment, a signal conversion device includes a first serial-parallel converter, a second serial-parallel converter, a first buffer, a second buffer, a clock generator, and a selection output part. The first serial-parallel converter receives a first serial signal, generates a first clock signal I, generates a first parallel signal, and generates first status information including first information. The second serial-parallel converter receives a second serial signal, generates a second clock signal, generates a second parallel signal, and generates second status information including second information. The first buffer stores the first parallel signal. The second buffer stores the second parallel signal. The clock generator generates an output clock signal. The selection output part uses the first status information and the second status information to output a signal based on one parallel signal of the first parallel signal or the second parallel signal.

A multiplexer (MUX) configured to receive a plurality of input data streams and output an output data stream via an output data line based at least in part upon a control signal, includes: a first circuit portion corresponding to a first data stream of the plurality of input data streams, comprising: a first internal node; a first control switch operable to connect the output data line to the first internal node of the first circuit portion based at least in part upon the control signal, wherein the first internal node has a value corresponding to the first data stream when the output data line is connected to the first internal node; and a first reset switch operable to connect the first internal node to a common mode voltage rail based at least in part upon the control signal to remove or reduce residual charge at the first internal node.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

An optical transceiver configured to operate in a host device includes an electrical interface communicatively coupled to the host device to interface electrically with the host device, wherein the optical transceiver is compliant with a Multi-Source Agreement (MSA) which is supported by the host device; optical transceiver components communicatively coupled to the electrical interface, wherein the optical transceiver components are configured to optically interface signals with a second optical transceiver to form an optical link; and electronic dispersion compensation circuitry communicatively coupled to the optical transceiver components and configured to electronically compensate for optical fiber chromatic and/or polarization mode dispersion associated with the optical link, separate and independent from the host device.

Integrated performance monitoring (PM); optical layer operations, administration, maintenance, and provisioning (OAM&P); alarming; amplification, and the like is described in optical transceivers, such as multi-source agreement (MSA)-defined modules. A pluggable optical transceiver defined by an MSA agreement can include advanced integrated functions for carrier-grade operation which preserves the existing MSA specifications allowing the pluggable optical transceiver to operate with any compliant MSA host device with advanced features and functionality, such as Forward Error Correction (FEC), framing, and OAM&P directly on the pluggable optical transceiver. The advanced integrated can be implemented by the pluggable optical transceiver separate and independent from the host device.

A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.