A system, method and computer product for performing a time synchronization between first and second nodes includes the first node performing: generating a synchronization message, transmitting the synchronization message to the second node at a first time, taking a first timestamp in response to the synchronization message being transmitted and transmitting a timestamp message including the first timestamp to the second node at a second time; and the second node performing: receiving the synchronization message and the timestamp message from the first node, taking a second timestamp in response to the synchronization message being received, receiving the timestamp message from the first node, obtaining the first timestamp based on the received timestamp message, obtaining a timing offset between the first timestamp and the second timestamp and performing a time synchronization to the first node based on the timing offset.

A method monitors a data transmission network having a plurality of devices connected to one another over fixedly prescribed signal transmission paths, for anomalies. One of the devices is a master device that has a counter and a trigger apparatus, by which a prescribed signal feature of a signal is acquired, and upon the acquisition, a master counter state corresponding thereto is read. The method provides for an evaluation apparatus to determine, under predetermined conditions, a setpoint value of at least one network-specific parameter defined by a physical property of the network, before an actual value of the network-specific parameter is determined from a difference between the master counter state and a further counter state, and an anomaly is indicated if a predetermined deviation criterion between the actual value and the setpoint value is met.

Systems and methods for one-way time transfer using physical layer signaling are disclosed herein. According to some examples, a method includes generating timing information based on a clock of a transmitting device, where the timing information comprises a timestamp and metadata. The method further includes generating a preamble of a frame, where the preamble includes the timestamp and the metadata of the timing information. The method also includes forming a frame, where the frame comprises a bootstrap, the preamble, and a payload, and transmitting the frame to a receiver device. The one-way time transfer systems and methods of this disclosure can serve mobile devices that entail quick and reliable establishment of a clock.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

A display method is for a display apparatus to display an image, and includes: obtaining a captured display image by an image sensor included in a terminal device; obtaining a light ID by visible light communication with a subject; obtaining an AR image and recognition information which are associated with the light ID from a memory included in the terminal device; recognizing a target region within the captured display image using the recognition information; and displaying the captured display image in which the AR image is superimposed on the target region.

A TDMA network device compatible with other networks is disclosed. It needs no additional control signals. Based on received data packets or data volume to process time synchronization and time division based on received data and prepared in advance, it is to ensure that every node can calculate approximate time allocation and pass the time division features to the next layer of network.

The present disclosure relates to systems and methods for clock synchronization. The system may include a reset signal generator connected with a plurality of detectors. The reset signal generator may be configured to generate a set of preliminary reset signals to be detected and transmit the set of preliminary reset signals to the plurality of detectors. Each of the set of preliminary reset signals may have a different phase. Each of the plurality of detectors may be configured to generate first feedback data for each of the set of preliminary reset signals and transmit the first feedback data to the reset signal generator. The reset signal generator may be further configured to generate, for each of the plurality of detectors, a reset signal based on the first feedback data and transmit the reset signal to each of the plurality of detectors. Each of the plurality detectors may be further configured to execute a clock synchronization in itself based on the reset signal.

The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.

A system, method and computer product for performing a time synchronization between first and second nodes includes the first node performing: generating a synchronization message, transmitting the synchronization message to the second node at a first time, taking a first timestamp in response to the synchronization message being transmitted and transmitting a timestamp message including the first timestamp to the second node at a second time; and the second node performing: receiving the synchronization message and the timestamp message from the first node, taking a second timestamp in response to the synchronization message being received, receiving the timestamp message from the first node, obtaining the first timestamp based on the received timestamp message, obtaining a timing offset between the first timestamp and the second timestamp and performing a time synchronization to the first node based on the timing offset.

A network device operative to maintain a first time of day (ToD) synchronized to a grandmaster clock is provided and includes a physical layer (PHY) circuit and a processor. The PHY circuit: maintains the first ToD in a first format and a second ToD in a second format; initially sets the second ToD based on a master ToD of the grandmaster clock; and updates the second ToD to maintain synchrony with a master time of the grandmaster clock by incrementing a counter based on a local clock, periodically updating the first ToD responsively to a counter value of the counter, and based on the updated first ToD and a compensation value, periodically adjusting the second ToD to more closely match the master time. The processor ascertains whether the second ToD has drifted from the master time and adjusts the compensation value based on whether the second ToD has drifted.