H04J3/0635

Data transmission method, communications device, and storage medium

A data transmission method includes: obtaining Q first code block streams, wherein Q is an integer greater than 1, the coding type is M1/N1 bit coding, and one code block in the first code block stream comprises a synchronization header area of (N1−M1) bits and a non-synchronization one code block in the second code block stream comprises a synchronization header area of (N1−M1) bits and a non-synchronization header area of M1 bits, and a non-synchronization header area of a code block in the Q first code block streams is carried in a non-synchronization header area of a code block in the second code block stream. header area of M1 bits; and placing non-synchronization header areas of code blocks in the Q first code block streams into a to-be-sent second code block stream, wherein a coding type of the second code block stream is M1/N1 bit coding.

METHOD OF OPERATING A DEVICE, DEVICE AND SYSTEM
20220221896 · 2022-07-14 ·

In a method for operating a device comprising an internal clock generator and an internal clock and being connected to a network, the internal clock is incremented by the internal clock generator. Moreover, the internal clock is synchronized with a network frequency of the network.

Link establishment between a radio equipment controller (REC) and radio equipment (RE) in a fronthaul network

Techniques associated with link establishment in a fronthaul network are described herein. In one embodiment, a method includes receiving, by a proxy node, a Common Public Radio Interface (CPRI) bit stream transmitted by a radio equipment controller, wherein the CPRI bit stream is transmitted within a transmit time interval of the radio equipment controller; and fast-sampling, by the proxy node, the CPRI bit stream to determine whether a hyper frame number synchronization with the radio equipment controller at a common matching link bit rate is achievable, wherein the fast-sampling comprises attempting to decode the received CPRI bit stream and achieve the hyper frame number synchronization for each of a plurality of link bit rates configured for a fast-sampling time period during at least one fast-sampling time interval configured for the proxy node.

Multi-chip synchronization in sensor applications

A system may include a plurality of actively-driven inductive sensors and a plurality of control circuits, each control circuit of the plurality of control circuits configured to control operation of a respective set of the actively-driven inductive sensors, each control circuit of the plurality of control circuits communicatively coupled to the other control circuits via a connection configured to distribute synchronization information among the plurality of control circuits. Each of the plurality of control circuits may further be configured to configure a schedule for controlling time-division multiplexed operation of its respective set of actively-driven inductive sensors and control time-division multiplexed operation of its respective set of actively-driven inductive sensors based on the schedule and the synchronization information in order to minimize interference among the plurality of actively-driven inductive sensors.

Clock synchronization in mesh networks

A method for maintaining synchronization of nodes in a mesh network includes: receiving primary beacons from a first transmitting node during a predetermined time interval, each of the primary beacons comprising time information indicating a time that a respective primary beacon was transmitted; comparing the time that each of the primary beacons was transmitted with a time that each of the primary beacons was received to determine a time difference; accumulating the time difference for each primary beacon received from the first transmitting node during the predetermined time interval to generate a first time synchronization error; comparing the first time synchronization error to a first threshold value; and in response to determining that the first time synchronization error exceeds the first threshold value, transmitting a first request to the first transmitting node to increase a rate of beacon transmissions for a specified period of time.

TIME SYNCHRONIZATION OF CONTROLLER

A controller includes circuitry configured to: synchronize a master clock with an external global clock and set a master time based on the master clock; synchronize a controller clock with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; transmit controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal for the time synchronization; determine whether one clock cycle of the plurality of clock cycles has started within one time window of the plurality of time windows, the one time window corresponding to the one clock cycle; and suspend the time synchronization corresponding to the one clock cycle, in response to determining that the one clock cycle has not started within the one time window.

SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION
20220079545 · 2022-03-17 · ·

The present disclosure relates to systems and methods for clock synchronization. The system may include a reset signal generator connected with a plurality of detectors. The reset signal generator may be configured to generate a set of preliminary reset signals to be detected and transmit the set of preliminary reset signals to the plurality of detectors. Each of the set of preliminary reset signals may have a different phase. Each of the plurality of detectors may be configured to generate first feedback data for each of the set of preliminary reset signals and transmit the first feedback data to the reset signal generator. The reset signal generator may be further configured to generate, for each of the plurality of detectors, a reset signal based on the first feedback data and transmit the reset signal to each of the plurality of detectors. Each of the plurality detectors may be further configured to execute a clock synchronization in itself based on the reset signal.

ALERT AND DISASTER MANAGEMENT SYSTEM AND METHOD FOR OPERATING SUCH A SYSTEM
20210273848 · 2021-09-02 ·

The alert and disaster management System (100) comprises: at least one radiocommunication terminal (105), the terminal comprising: a means (106) for communicating, via a data network, with a central computer system, —a sensor (110) for sensing a value of a physical variable that is representative of the operation of the network connected to the terminal, a means (115) for determining a network failure according to the captured value, a transmitter (120) of radio signals in the event a failure is determined and —the central computer system (300), connected via the data network to at least one terminal, comprising: a memory (304) of geographical positioning information of at least one terminal, a detector (305) for detecting network connection anomalies between the computer system and at least one terminal, a means (310) of providing an alert in the event of an anomaly, a means (315) of providing a piece of information that represents the stored positioning of at least one said terminal having a network connection anomaly and at least one mobile radiocommunication receiver (125) configured to receive the radio signals transmitted by at least one terminal.

Communication system, communication device and communication method
11095382 · 2021-08-17 · ·

A communication system according to one aspect of the present disclosure is a communication system in which a plurality of communication devices are connected to a network. The plurality of communication devices include a time master including a master clock that manages time of the communication system and a plurality of time slaves each of which includes a slave clock time-synchronized with the master clock. Each of the plurality of time slaves includes a synchronization unit that performs time synchronization with another communication device connected adjacent to a master side on the network and a communication unit that notifies the time master of time synchronization information indicating time synchronization accuracy of the own device obtained by the synchronization unit.

Systems and Methods for Digital Synthesis of Output Signals Using Resonators
20210175889 · 2021-06-10 · ·

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.