A receiver includes a feed-forward equalizer, a first detector, a jitter estimation circuit, and a jitter mitigation circuit. The feed-forward equalizer is configured to equalize channel gain of digitized samples of a received signal and to output equalized samples. The first detector is configured to detect symbols in the equalized samples. The jitter estimation circuit is configured to estimate jitter in the equalized samples by estimating a deviation in periodicity between pairs of the equalized samples. The jitter mitigation circuit comprises a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference.

Each of wearable terminals includes a terminal time correction unit configured to correct terminal time of a terminal clock unit based on time data externally acquired, a terminal data generation unit configured to generate terminal data at a predetermined data generation time interval counted based on an output signal of an oscillation circuit, and a data transmission/reception unit configured to transmit the terminal data to an analysis apparatus. The analysis apparatus includes a terminal data correction unit configured to correct, for each of the wearable terminals, terminal time data of the plurality of pieces of terminal data received from each of the wearable terminals. The terminal data correction unit corrects the terminal time data of the plurality of pieces of terminal data in such a way that intervals between the terminal time data of the plurality of pieces of terminal data become even on the time axis.

The present invention discloses a signal communication method having re-sampling mechanism that includes steps outlined below. Sampled data of a data signal is obtained. A time difference between an actual sampling time point and an ideal sampling time point is calculated. A closet time point closest to the ideal sampling time point within a sampling time interval is selected. Operation sampled data within a predetermined range around the target sampled data is selected from the sampled data. A group of response terms are retrieved from a pre-stored lookup table according to the closest time point to substitute the response terms and the time difference into a parameter calculation equation to generate a group of re-sampling response parameters. A calculation is performed based on the operation sampled data and the re-sampling response parameters to generate a re-sampled value of the target sampled data.

A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.

A coherent optical receiver includes equalizer circuitry having a plurality of taps, the equalizer circuitry being configured to receive an input signal and compensate for polarization mode dispersion affecting the input signal to generate a compensated input signal. The coherent optical receiver further includes error evaluation circuitry configured to calculate a determinant of a frequency-domain (FD) coefficient-based matrix using a plurality of tap signals from among the plurality of taps, adjust an error of convergence of the compensated input signal to generate an adjusted input signal, and iteratively adjust the determinant of the FD coefficient-based matrix based on the adjusted input signal to minimize the error of convergence.

A receiver includes a feed-forward equalizer, a first detector, a jitter estimation circuit, and a jitter mitigation circuit. The feed-forward equalizer is configured to equalize channel gain of digitized samples of a received signal and to output equalized samples. The first detector is configured to detect symbols in the equalized samples. The jitter estimation circuit is configured to estimate jitter in the equalized samples by estimating a deviation in periodicity between pairs of the equalized samples. The jitter mitigation circuit comprises a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.