A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

A signal interpolation method is described. The method includes: receiving an analog input signal; digitizing the analog input signal received, thereby obtaining a digitized input signal having samples; determining a crossing of the digitized input signal with respect to a threshold that was set; and interpolating a signal between at least two successive samples, wherein the signal interpolated has two signal portions each having a linear slope, and wherein one of the signal portions crosses the threshold. A measurement instrument is also described.

A method for transmitting data by using a power line. The method includes: setting i=1 and j=1; receiving an i-th zero crossing signal at a time point ti, and determining, based on the i-th zero crossing signal, a start time when synchronization signals of a j-th data packet are transmitted, the start time when the synchronization signals of the j-th data packet are transmitted being t.sub.i+t; transmitting the synchronization signals of the j-th data packet at the start time when the synchronization signals of the j-th data packet are transmitted; transmitting data signals of the j-th data packet in sequence; and determining whether j is equal to M; when j is not equal to M, continuing a data transmission; and when j is equal to M, ending the data transmission, M being a number of data packets into which data to be transmitted is divided.

A method for synchronizing signals of a plurality of participants. A relationship between the signals is given by a physical relation. The signals are each filtered with a first filter in order to determine a shift between the signals. The determined shift is a measure of the phase shift between the signals. The shift is subsequently eliminated by filtering the signals respectively with a second filter.

The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.

The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

The present invention relates to a multi-channel IM-DD optical transceiver comprising at least one transmitter and a receiver, and a method for equalizing input samples at an adjusted sampling phase using a quality parameter linearly proportional to a BER. The data transmission and reception use a single master channel and slave channels, which have a baud rate equal to or lower than the baud rate of the master channel. A reliable and identical clocking of all the channels is obtained through either the receiver clock of the master channel when they are received from a single transmitter or a reference clock whose frequency is higher than the highest clock frequency amongst all the channels when they are received from a combination of transmitters. An enhanced timing recovery circuit is also provided to select optimized finite impulse response filters, calculate filter coefficients and generate the receiver clock of the master channel.