Disclosed are a device and method for realizing data synchronization. The device may include a synchronization circuit for a plurality of radio frequency (RF) chips, configured to realize work clock synchronization among the plurality of RF chips; and/or, a synchronization circuit for a plurality of channels in a single chip, configured to realize data synchronization among the plurality of channels in the single chip.

A clock generator circuit includes: first to N.sup.th nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to N.sup.th nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to N.sup.th nodes have a first level, and the signals of odd-numbered nodes among the first to N.sup.th nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to N.sup.th nodes have the same level.

The present technology relates to a signal processing device, a signal processing method, and a program capable of reducing influence of crosstalk. Provided are: a plurality of comparators; a delay unit adapted to delay output of each of the plurality of comparators; and a subtractor adapted to subtract, from a supplied signal, a signal from the delay unit. The signal processing device processes signals transmitted in N phases and includes (N−1) or more comparators. Each of the plurality of comparators has a different threshold value set and compares a received signal with the threshold value, and in a case where the signal transitions between a plurality of voltage levels, the threshold value is set to a value within adjacent voltage levels. The present technology can be applied to a reception device that receives a signal transmitted in multiple phases and via multiple lines.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A method and a structure for determining a global clock among systems are disclosed. When a standardized time reference is required among systems, a reference clock source may transmit a calibration signal, and a transmitting time T.sub.d (0) may be recorded. Each system may respectively record an arrival time T.sub.a (n), transmit a return signal to a signal recording unit of the reference clock source, and record a transmitting time T.sub.b (n), after receiving the calibration signal. Similarly, because of different distances, the signal recording unit may record arrival times T.sub.d (n) of the return signals subsequently, and determine time delays Delay (n) between systems and the reference clock source respectively. When all the systems are required to have a completely standardized time reference, a corresponding Delay (n) may be acquired and transmitted to each system. Each system may determine zero deviations T.sub.c (n) of various local clocks from the reference clock source, and take T.sub.c (n) as a correction parameter to correct its own system clock, so that the local clocks of all the systems have a completely standardized time reference.

A computer-implemented method for synchronizing nodes on a controller area network includes identifying, via a processor, a node from a plurality of nodes as a sync master node; designating, via the processor, each of the remaining nodes as a sync slave node; designating, via the processor, the first message from the sync master node as a sync message; assigning, via the processor, the lowest number, among all the message IDs in the network system, to the message ID of the sync message; determining a sync message target receiving time on a sync slave node; and triggering an interrupt to the processor responsive to receiving the sync message on a sync slave node in the controller area network to perform time adjustment on the sync slave node.

In a control system, a controller and a plurality of input/output units are daisy-chained, and each of the input/output units detects a phase difference between a phase of received serial data and a phase of a reference clock, outputs a determination signal if the phase difference exceeds a threshold value, and records the output frequency of the determination signals. The controller acquires the frequency of the determination signals recorded by each of the input/output unit and specifies a noise mixture route based on the acquired frequency of the determination signals.

A control circuit of a communication device includes: a periodic packet detection circuit, detecting a periodic packet of a data signal to generate a packet indication signal corresponding to the periodic packet; a frequency synthesis circuit, coupled to the periodic packet detection circuit, generating a working clock according to a reference clock; and a setting value generating circuit, coupled to the periodic packet detection circuit, generating a setting value according to a relationship between the frequencies of the working clock and the packet indication signal. The frequency synthesis circuit further adjusts the working clock according to the setting value to cause the frequency of the working clock to substantially be a predetermined multiple of the frequency of the packet indication signal.

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

A system and method are described for calibrating a clock used in data transmission. In one example, dynamic phase adjustment circuitry can be used for any of a variety of different protocols to shift the clock phase with respect to a data signal. In the most typical example, the clock phase is shifted 90 degrees relative to a transmission data signal. The dynamic phase adjustment circuitry can use two cascaded programmable delay lines coupled in series. Each programmable delay line represents a half phase delay of 90 degrees. A controller can monitor an output of the programmable delay lines and incrementally add or subtract programmable delay line elements until a 180 degree phase is detected relative to a data transmission. An output clock can then be used by applying the result of the calibration delay element to the clock under discussion.