Disclosed is a modulation method for modulating n-bit data (n=p+q+r). The modulation method includes forming a time difference between a data impulse and a sync impulse to correspond to p-bit data, modulating the amplitude of the sync impulse to correspond to q-bit data and modulating the amplitude of the data impulse to correspond to r-bit data, and combining the sync impulse and the data impulse. As an example, n may be equal to p+q+r.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

A method may include receiving, from an endpoint device, a request to register a service that is supported by the endpoint device, identifying, in view of the service identified in the request, a service provider of interest that relates to the service, receiving, from the endpoint device, a service connection request to initiate data flow related to the service, validating the endpoint device, and responsive to validating the endpoint device, establishing the service connection to a device associated with the service.

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.

A signal divider includes: a dividing circuit arranged to generate an output oscillating signal according to a first input oscillating signal; and a signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit. The dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal.

The present technology relates to a signal processing device, a signal processing method, and a program capable of reducing influence of crosstalk.

Provided are: a plurality of comparators; a delay unit adapted to delay output of each of the plurality of comparators; and a subtractor adapted to subtract, from a supplied signal, a signal from the delay unit. The signal processing device processes signals transmitted in N phases and includes (N−1) or more comparators. Each of the plurality of comparators has a different threshold value set and compares a received signal with the threshold value, and in a case where the signal transitions between a plurality of voltage levels, the threshold value is set to a value within adjacent voltage levels. The present technology can be applied to a reception device that receives a signal transmitted in multiple phases and via multiple lines.