A circuit for estimating a time difference between a first signal and a second signal includes a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

The present invention relates to a network packet broker device including a deep packet matching module which controls a GTP correlation module to match a GTP control plane packet and a GTP user plane packet and a deep packet matching method thereof. Packet information in a deep stage at a switch level is extracted to match flows of the GTP control plane packet and the GTP user plane packet and a correlation may be assigned to forward the GTP control plane packet and the GTP user plane packet to the same egress port.

Methods, systems, and apparatus for EM communications. One of the apparatus includes a super-regenerative amplifier (SRA) configured to receive a binary phase shift keying (BPSK) modulated signal and to output an amplitude signal as a function of changes in phase in the BPSK modulated signal; a pseudo synchronous demodulator that rectifies the amplitude signal and generates an envelope of the rectified amplitude signal; and an analog to digital converter that converts the amplitude values of the envelope to digital binary values.

A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

A method for configuring a time division duplex (TDD) of a user equipment in a communication system, according to one embodiment of the present invention, comprises the steps of: receiving from a base station a first TDD configuration; receiving from the base station a message including information related to a dynamic TDD configuration; receiving a second TDD configuration according to the received information related to the dynamic TDD configuration; receiving from the base station an uplink grant; and determining whether to apply the first TDD configuration or the second TDD configuration based on a method by which the unlink grant is received. According to one embodiment of the present invention, the advantages of configuring a shorter cycle of the TDD to the user equipment supporting the TDD in a wireless communication system, and rapidly configuring the TDD to the user equipment variably according to a communication situation are provided.

An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.

A master node of a distributed acquisition system is provided. The master node includes a communication interface for interfacing between a control component and a bus and the control component. The bus is coupled to one or more slave nodes distributed in the acquisition system. The control component is configured to acquire a configuration that provides a definition for a packet interval, wherein the packet interval definition provides an adequate timing margin to ensure that communication packets transmitted by the master node and the one or more slave nodes occur only at harmonics of the packet interval definition, distribute a time reference packet of the communication packets based on the packet interval definition via the bus to all of the slave nodes of the distributed acquisition system, and schedule transmission of communication packets transmitted by the master node via the bus to the one or more selected slave nodes based on the packet interval definition.

Certain examples described herein provide a method for providing a collaborative session over a network. In these examples, a collaborative session is a series of geographically-separated temporally-coordinated events, such as a performance or concert. In examples, a global latency is set for the collaborative session. The global latency is set to a value greater than a longest latency for a plurality of client devices engaging in the collaborative session, and is defined as a function of a temporal rate for the series of temporally-coordinated events. During the collaborative session data streams are received from the plurality of client devices and presentation of the received data streams on the plurality of client devices is synchronised to enforce the global latency.

A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

Provided is a node unit which is branch-connected to another communication node via a transport medium, the node unit comprising: a delay measurement unit which transmits a test signal for measuring a delay to an adjacent node unit of the branch-connected upper stage via the transport medium and detects a loopback signal to which the test signal is looped back via the adjacent node unit of the upper stage, thereby measuring an upper stage transmission delay between the adjacent node unit of the upper stage and the node unit; a delay summation unit which, when an adjacent node unit of the branch-connected lower stage exists, receives a lower stage transmission delay transmitted from the adjacent node unit of the lower stage, and calculates a summed transmission delay by summing the upper stage transmission delay and the lower stage transmission delay; and a control unit which transmits the summed transmission delay to the adjacent node unit of the upper stage.