It must be understood that such structure comprising CP1 and CS1 is implicitly there, even if the transmitter only explicitly prepends a CP1. Indeed, and explained by example of a full duplex multicarrier system, the receiver will still be required to discard a number of samples equivalent to a cyclic suffix from the received time samples of each symbol to obtain orthogonality with the echo received from the transmit symbols.

According to one embodiment, an electronic device executes decision feedback-type equalization for input data using a tap coefficient while updating the tap coefficient. The electronic device includes a first memory cyclically receiving a tap coefficient, holing the tap coefficient received, and cyclically outputting the tap coefficient held, and a second memory receiving the tap coefficient cyclically output from the first memory and holding the tap coefficient received. The tap coefficient cyclically output from the first memory is delayed by at least one cycle than the tap coefficient cyclically received by the first memory. The tap coefficient held in the second memory is used for the decision feedback-type equalization in a no-signal period in which no input data exist.

This VR viewing system is configured such that an external computer 200 outputs sound from an external speaker 300 while an HMD 100 reproduces a VR moving image by means of a built-in computer. The external computer 200 performs a sound output to the external speaker 300, conducts a master management of a reproduction elapsed time of the VR moving image so as to be synchronized with the sound output, detects a difference between the reproduction elapsed time of the VR moving image by the built-in computer of the HMD 100 and the reproduction elapsed time of the VR moving image undergoing the master management by the external computer 200, and adjusts the reproduction of the VR moving image by the built-in computer so as to eliminate the detected difference.

A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

A receiver includes a first receiving circuit that receives a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals. The first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

The application discloses Systems and methods for a data synchronization. The system may include a receiving module, an instruction generating module and a sending module. The receiving module may be configured to receive the first instruction. The first instruction may be used to instruct the start of data acquisition of the system. In response to receiving the first instruction, the instruction generating module may be configured to generate a second instruction. The second instruction may be used to trigger at least two sensors to acquire data. The sending module may be configured to send second instruction to at least two sensors respectively based on the first delay. The first delay causes the time difference between at least two sensors starting to acquire data less than the first preset threshold.

Provided is a node unit which is branch-connected to another communication node via a transport medium, the node unit comprising: a delay measurement unit which transmits a test signal for measuring a delay to an adjacent node unit of the branch-connected upper stage via the transport medium and detects a loopback signal to which the test signal is looped back via the adjacent node unit of the upper stage, thereby measuring an upper stage transmission delay between the adjacent node unit of the upper stage and the node unit; a delay summation unit which, when an adjacent node unit of the branch-connected lower stage exists, receives a lower stage transmission delay transmitted from the adjacent node unit of the lower stage, and calculates a summed transmission delay by summing the upper stage transmission delay and the lower stage transmission delay; and a control unit which transmits the summed transmission delay to the adjacent node unit of the upper stage.

A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.

The present invention relates to a network packet relay device including a time synchronization module for synchronizing a time of a packet with a timestamp value of a network device, and a packet timestamp assigning method thereof, wherein a timestamp having accuracy of a UTC-format nanosecond level can be assigned to the packet at a hardware level by correcting overflow of a register of an elapsed-time counter of a processor of a switch even when the overflow occurs.