An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine a guard period associated with switching from a first communication mode to a second communication mode. The UE may be operating in a half-duplex frequency division duplexing mode of operation. The guard period may be determined based at least in part on at least one of: a number of phased locked loops to be used for the first communication mode and the second communication mode, and a particular subcarrier spacing associated with the UE. The UE may switch from the first communication mode to the second communication mode based at least in part on the guard period. Numerous other aspects are provided.

A system and method are provided for measuring residual phase noise of a measurement signal using a phase detector including a mixer. The method includes injecting a phase noise spur in a stimulus signal having a known magnitude at a known offset frequency from the stimulus signal carrier frequency; inputting the stimulus signal to a DUT to output a measurement signal; inputting the measurement signal to RF input of the mixer via RF path; inputting the stimulus signal to LO input of the mixer via LO path; mixing the measurement and stimulus signals to provide a residual phase noise signal; measuring actual rejection of stimulus phase noise at the know offset frequency; determining a relative delay between the measurement and stimulus signals in the RF and LO paths based on the actual rejection; and minimizing relative delay between the measurement and stimulus signals to reduce residual phase noise measurement floor.

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

A slave device (10) includes a frequency synchronization unit (11) configured to generate frequency control information synchronized with a frequency of a synchronous Ethernet (registered trademark) signal received from a master device (20), a time synchronization unit (12) configured to generate time control information synchronized with a time based on a time packet received from the master device (20), and a time synchronization signal generation unit (13) configured to generate a time synchronization signal based on the frequency control information and the time control information. The frequency synchronization unit (11) includes a frequency synchronizing PLL including a DCO (11a) configured to output the frequency control information, and the time synchronization unit (12) includes a time synchronizing PLL including a DCO (12a) configured to output the time control information.

Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

Provided are methods for optical communication, comprising: generating a phase difference signal with heterodyne or homodyne phase-locked-loop (PLL) from between an optical input signal and a local laser source; controlling the local laser source with the phase difference signal; demodulating the optical input signal using the local laser source as a carrier signal to generate a baseband output signal; and controlling the heterodyne or homodyne PLL and the demodulation with an electrical oscillator signal. Also provided are related methods.

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

The present invention provides methods for a high-resolution active RTLS tag location determination system that provides for <1 ns TOA accuracy and resolution and significantly reduces the channel effects of multipath interference, even in low SNR applications. To accomplish these objectives, the present invention provides for an iterative and adaptive windowing function in each of the receivers of a receiver grid that captures multiple reflections of multiple transmissions from each of the associated target RTLS tags. The adaptive windowing function is used in conjunction with an asynchronous transmit and receive clock function that effectively increases resolution of TOA detection to levels less than the minimum detection window width associated with each of the receivers in the receiver grid.