The invention relates to a method for transmitting an actuation signal and a first data signal between a control device and an actuation device of a power semiconductor device. To minimize the expenditure for the operation of the physical transmission channels and the costs for the laying of the physical connection between control device and actuation device, the transmission of the actuation signal and the first data signal between the control device and the actuation device takes place simultaneously and via a common transmission channel, wherein the first data signal is combined with the actuation signal by means of a digital modulation method or coding method. A feedback signal and second data signal are transmitted in the opposite direction. A first coding length is shorter than the interval length of the actuation signal. A second coding length is shorter than the interval length: of the feedback signal.

Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.

In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.

A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

A method and apparatus for generating a probability density function eye are provided. The method preferably includes the steps of acquiring an input waveform, performing a clock data recovery in accordance with the input waveform to determine one or more expected transition times and defining a plurality of unit intervals of the input waveform in accordance with the one or more expected transition times. One or more values of one or more data points may then be determined in accordance with the input waveform in accordance with the one or more expected transition times, and a category for each unit interval in accordance with its state and its position within the input waveform may also be determined. One or more histograms may then be generated for the determined one or more values for each category of unit intervals.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

The Direct Synthesis of a Receiver Clock (DSRC) contributes a method, system and apparatus for reliable and inexpensive synthesis of inherently stable local clock synchronized to a referencing signal received from an external source. Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver. Such DSRC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI or Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.

A method includes computing electrical phase of electrical metering devices including obtaining data indicating zero-crossing times at first and second metering devices. A time difference between the zero-crossing times may be determined. In a first example, the time difference may be based at least in part on calculations involving a first value of a first free-run timer on a first metering device, a second value of a second free-run timer on a second metering device, the time of reception of a packet, and a latency defined by a time taken for the packet to propagate through at least one layer of at least one of the first metering device and the second metering device. A phase difference between the first zero-crossing and the second zero-crossing may be determined, based at least in part on the determined time difference.