An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

A sensor subassembly having a memory unit for storing a sensor data value from the sensor subassembly and a transmission unit for sending a data signal with information about the stored sensor data value to an external receiver at a data rate that is dependent on a clock frequency of a clock signal produced by the sensor subassembly. The transmission unit sends the data signal with the information about the stored sensor data value on the basis of a piece of trigger information in an externally received control signal.

A source-synchronous system is provided in which a master device is configured to vary the phase between a transmitted data signal and a corresponding source-synchronous clock to measure the margins of a data eye at a slave device.

A wireless communication apparatus has an analog control loop circuitry to generate an analog control signal which adjusts a phase of a voltage-controlled oscillation signal, an integrator to integrate the analog control signal, a phase adjuster to adjust a phase of the voltage-controlled oscillation signal, a digital control loop circuitry, in a first mode, to match a frequency of the voltage-controlled oscillation signal to a frequency of the received signal based on an output signal of the phase adjuster, and in a second mode, to generate a digital control signal which is opposite in phase to the analog control signal and has a frequency, a voltage-controlled oscillator to generate the voltage-controlled oscillation signal based on the analog and digital control signals, and a signal switch to supply the analog control signal to the integrator in the first mode and to the voltage-controlled oscillator in the second mode.

A digital system of measuring parameters of the signal (phase, frequency and frequency derivative) received in additive mixture with Gaussian noise. The system is based on the use of variables of a PLL for calculating preliminary estimates of parameters and calculating the corrections for these estimates when there is a spurt frequency caused by a receiver motion with a jerk. A jerk is determined if the low pass filtered signal of the discriminator exceeds a certain threshold. The jerk-correction decreases the dynamic errors. Another embodiment includes a tracking filter for obtaining preliminary estimates of parameters to reduce the fluctuation errors. Estimates are taken from the tracking filter when there is no jerk and from the block of jerk-corrections when there is a jerk.

A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

A digital system of measuring parameters of the signal (phase, frequency and frequency derivative) received in additive mixture with Gaussian noise. The system is based on the use of variables of a PLL for calculating preliminary estimates of parameters and calculating the corrections for these estimates when there is a spurt frequency caused by a receiver motion with a jerk. A jerk is determined if the low pass filtered signal of the discriminator exceeds a certain threshold. The jerk-correction decreases the dynamic errors. Another embodiment includes a tracking filter for obtaining preliminary estimates of parameters to reduce the fluctuation errors. Estimates are taken from the tracking filter when there is no jerk and from the block of jerk-corrections when there is a jerk.