A method for recovering a clock signal from a data signal by using a clock recovery module is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module as well as a computer program are described.

A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

The present disclosure relates to system(s) and method(s) for multi-level amplitude modulation and demodulation. The system accepts a frame delimiter signal, when a comparator is triggered upon receiving the frame delimiter signal from a transmitter. Further, the system receives modulated data associated with a data frame from the transmitter. In one aspect, the modulated data may be generated by modulation of the data frame using a set of three amplitude levels. Upon receiving the modulated data, the system demodulates the modulated data to retrieve the data frame along with the frame delimiter signal, which can be used for successive digital logic elements for enhanced performance.

A clock and data recovery device includes an extraction circuit and a phase detection circuit. The extraction circuit extracts transition information including data information corresponding to a value of data and edge information corresponding to transition of the value of the data, from a multivalued input data signal subjected to pulse amplitude modulation in synchronization with a clock from an oscillator. The phase detection circuit uses transition information selected based on a predetermined condition, when executing a phase error determination of the clock with respect to the input data signal based on the transition information extracted by the extraction circuit.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

A method for monitoring an RF receiver includes generating of a digital test signal based on a signal, wherein the digital test signal includes a stream of digital test samples having a digital test sample; generating a monitoring signal based on the digital test signal; and coupling of the monitoring signal into a receiver path. The monitoring signal is processed in the receiver path to generate a processed monitoring signal and a stream of digital monitoring samples representing the processed monitoring signal. Information is determined indicating at least one property related to the receiver path based on a processing of a set of digital monitoring samples of the stream of digital monitoring samples. The set of digital monitoring samples includes a digital monitoring sample. The method further includes controlling the RF receiver such that the digital monitoring sample is generated a predetermined time duration after generating the digital test sample.

A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.