Patent classifications
H04L7/042
SYNCHRONIZATION TIMING DETECTOR, WIRELESS COMMUNICATION DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM
A synchronization timing detector includes n correlators, a calculation unit, and a symbol timing estimating unit. The n correlators calculate and output correlation values, between a received signal oversampled m times for one symbol period and a known synchronization pattern, by shifting sample timings by m/n samples each, where m is a natural number, and n is a natural number that satisfies 3≤n≤m and is a divisor of m. The calculation unit generates n correlation value vectors by arranging the correlation values output from the n correlators on polar coordinates at intervals of an angle of 2π(n/m) radians, and adds the n correlation value vectors to calculate an angle of a resultant vector of the correlation value vectors. The symbol timing estimating unit estimates a symbol timing of the received signal based on the angle of the resultant vector calculated by the calculation unit.
Variable rate sampling for AGC in a bluetooth receiver using connection state and access address field
A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.
Frame synchronization apparatus, optical communication apparatus, and frame synchronization method
A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high.
APPARATUS AND METHOD OF CONTROLLING A MULTI-ANTENNA COMMUNICATION SYSTEM
A method of controlling a multi-antenna communication system includes: obtaining a first baseband signal through a first antenna; performing a cross-correlation calculation on the first baseband signal and default information during a period of time, thereby to obtain a plurality of cross-correlation calculation results; calculating energy of the first baseband signal to obtain a first energy value; determining connectivity state of the first antenna according to the first energy value and the cross-correlation calculation results; and controlling a signal processing circuit of the multi-antenna communication system according to the connectivity state of the first antenna.
Receiving apparatus, receiving method, computer readable medium storing receiving program, and manufacturing method
A receiving apparatus is provided, including: a receiving unit to receive a plurality of pulses including a synchronization pulse and a data pulse having a data pulse width corresponding to a data value; a searching unit to search for pulse information indicating a pulse period or the like that falls within a synchronization pulse acceptable range from among pulse information indicating pulse periods or pulse widths of the respective pulses; a detecting unit to detect whether pulse information of a second pulse at a predetermined location relative to a first pulse corresponding to the searched pulse information indicates a pulse period or the like that falls within a data pulse acceptable range; an identifying unit to identify the first pulse as the synchronization pulse on condition that the pulse information of the second pulse indicates a pulse period or the like that falls within the data pulse acceptable range.
TECHNIQUES FOR UNIFIED SYNCHRONIZATION CHANNEL DESIGN IN NEW RADIO
Various aspects described herein relate to techniques for synchronization channel design and signaling in wireless communications systems (e.g., a 5th Generation (5G) New Radio (NR) system). In an aspect, a method includes identifying a frequency band supported by a user equipment (UE), identifying one or more frequency locations based on the identified frequency band, and the one or more frequency locations are a subset of synchronization raster points used for synchronization signal transmission. The method further includes searching for at least one synchronization signal based on the one or more identified frequency locations.
Adaptive Payload Extraction in Wireless Communications Involving Multi-Access Address Packets
Adaptive payload extraction in wireless communications involving multi-access address packets are described herein. A device can be configured to detect a synchronization sequence of a nested data packet, the nested data packet having synchronization sequences placed in series ahead of a payload, the synchronization sequences including the synchronization sequence; evaluate blocks after the synchronization sequence in the nested data packet to identify the blocks as either additional ones of the synchronization sequences or the payload in the nest data packet; and extract the payload.
Synchronisation symbol detector
A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.
Systems and methods for communicating by modulating data on zeros in the presence of channel impairments
Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.
Bi-phase communication demodulation techniques
One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.