In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

Transmitters and communication systems are disclosed. In one example, a transmitter includes first to third serializers that generate first to third serial signals; a first output section configured to set a voltage of a first output terminal; a first output control circuit configured to control an operation of the first output section on the basis of the first serial signal and the second serial signal; a second output section configured to set a voltage of a second output terminal; a second output control circuit configured to control an operation of the second output section on the basis of the third serial signal and the first serial signal; a third output section configured to set a voltage of a third output terminal; and a third output control circuit configured to control an operation of the third output section on the basis of the second serial signal and the third serial signal.

This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. The data link is initiated with the full data path and a first sequence of data packets is transferred via the full data path in accordance with a low data rate setting. While transferring the first sequence of data packets, the first sequence of data packets is manipulated in the full data path to establish a connection of the data link, and in response to establishing the connection of the data link, the data link is switched from the full data path to the bit level data path.

A biomedical signal sensing circuit including a first and a second modulation unit, an amplifying unit, a first and a second demodulation unit is provided. The first modulation unit performs a first modulation operation to a first biomedical signal according to a first signal to generate a first modulation signal. The second modulation unit performs a second modulation operation to a second biomedical signal according to a second signal to generate a second modulation signal. The amplifying unit amplifies the first and second modulation signals, and adds the amplified first and second modulation signals to generate a third modulation signal. The first demodulation unit performs a first demodulation operation to the third modulation signal according to the first signal to generate a first sensing signal. The second demodulation unit performs a second demodulation operation to the third modulation signal according to the second signal to generate a second sensing signal.

A transceiver of the present inventive concept includes a transmitter and a receiver connected by a first line and a second line, and the transmitter includes a first encoder; a second encoder; and a transmission driver. The first encoder generates a first encoded data different from a first data during a first period and the second encoder generates a second encoded data equal to a second data during the first period, the second encoder generates the second encoded data different from the second data during a second period and the first encoder generates the first encoded data equal to the first data during the second period, and the first period and the second period are arranged to alternate with each other.

A bidirectional isolated communication circuit and method for a differential signal. The circuit comprises a first detection circuit used for receiving a first differential pair from a first direction, converting the first differential pair into a first level signal, and inhibiting common-mode interference; a second detection circuit used for receiving a second differential pair from a second direction, converting the second differential pair into a second level signal, and inhibiting common-mode interference; an isolation adjustment circuit used for being provided between the first detection circuit and the second detection circuit and performing communication isolation; and a watchdog circuit used for being awoken according to the first differential pair and/or the second differential pair, and enabling the bidirectional isolated communication circuit to enter from a small current working mode to a normal working mode to perform communication isolation.

The disclosure provides a receiver and an automatic offset cancellation (AOC) method thereof. The receiver includes a receiving channel circuit and an AOC circuit. The receiving channel circuit generates an equalized differential signal including an equalized first-end signal and an equalized second-end signal according to an input differential signal. The AOC circuit detects a peak of the equalized first-end signal to generate a first peak detection result. The AOC circuit detects a peak of the equalized second-end signal to generate a second peak detection result. The AOC circuit compares the first peak detection result with the second peak detection result to generate a comparison result. The AOC circuit compensates a mismatch of an input differential pair in the receiving channel circuit according to the comparison result.

A measurement task is selected, where the measurement task is associated with a transmission of an encoded signal transmitted via a plurality of data lines. The encoded signal is encoded using one or more of 3-Phase, N-Phase, or N-factorial low-voltage differential signaling (LVDS) where N is at least three (3). A repeating waveform is generated corresponding to the measurement task. The repeating waveform corresponding to the measurement task is then transmitted via the plurality of data lines.

A configurable serial link interface circuit includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. The first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.