A power feeding apparatus is provided. The power feeding apparatus includes a power feeding unit configured to supply electric power to a power receiving apparatus through a magnetic field; a measuring unit configured to measure an electric characteristic value and to generate a measurement value; a power receiving unit configured to provide a set value; and a foreign substance detection unit configured to detect a foreign substance in the magnetic field based on the set value and the measurement value. A power receiving apparatus, a power feeding system, and a method of controlling power feeding are also provided.

The invention relates to a method of cancelling noise present in a data signal received on an electrical bifilar line (L), implemented by a sender-receiver device (M) comprising a first transformer (TD), termed the differential mode circuit, comprising a primary side (TDp) and a secondary side (TDs), the primary side being connected by two wires to the bifilar line, a second transformer (TC), termed the common mode circuit, comprising a primary side (TCp) and a secondary side (TCs), the primary side being connected by a wire (c) to the primary side (TDp) of the differential mode circuit, and to an earth by another wire, the method comprising the following steps during an adjustment phase: obtaining a first value of voltage on the bifilar line, termed the differential mode voltage; obtaining a second value of voltage corresponding to a voltage at the level of the two wires of the secondary side of the common mode circuit, termed the image voltage of the common mode, resulting from said differential mode voltage; calculating the ratio between the second value and the first value, termed the noise conversion ratio; and the method comprising the following steps during a cancellation phase, subsequent to the adjustment phase; receiving the data signal originating from the bifilar line; simultaneously with the receiving step, obtaining a third value corresponding to the voltage at the level of the two wires of the secondary side of the common mode circuit; cancelling the noise in the data signal, by subtracting an estimation of the noise, the estimation being calculated by dividing the third value by said conversion ratio.

A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.

A transmission device of the disclosure includes: a generator unit that generates, on the basis of a control signal, a transmission symbol signal that indicates a sequence of transmission symbols; an output control unit that generates an output control signal on the basis of the transmission symbol signal; and a driver unit that generates, on the basis of the output control signal, a first output signal, a second output signal, and a third output signal. The generator unit generates the transmission symbol signal on the basis of the control signal, to allow the first output signal, the second output signal, and the third output signal to exchange signal patterns with one another.

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

A battery monitoring system that monitors states of a plurality of batteries. The battery monitoring system includes a battery monitoring ECU and a plurality of battery monitoring devices. The battery monitoring ECU and the plurality of battery monitoring devices are connected to each other in any connection form of ring connection, daisy chain connection, or multi-drop connection.

Described herein is a fully-differential receiver for use with an implantable medical device (IMD) and configured to receive conducted communication signals that are transmitted by another IMD or an external device. The fully-differential receiver includes a fully-differential preamplifier, a fully-differential buffer, a first comparator, a second comparator, and an AC coupling network coupled between differential outputs of the fully-differential buffer and a coupled together differential pair of inputs of the first and second comparators. A differential pair of inputs of the fully-differential receiver comprise the differential pair of inputs of the fully-differential preamplifier, and a differential pair of outputs of the fully-differential receiver comprise a first output of the first comparator and a second output of the second comparator. In order to conserve power, the fully-differential receiver is selectively changed from operating in a first mode to operating in a second mode, and vice versa.

A frequency diverse distributed Mach-Zehnder Interferometer may include an optical modulator on a chip, with the modulator comprising a plurality of diodes arranged along a waveguide and with each diode driven by two or more drivers. An optical signal may be received in the waveguide, and a first modulating electrical signal may be applied to a first of the plurality of diodes using a first driver and a second modulating electrical signal may be applied to the first of the plurality of diodes using a second driver. The first electrical signal may be different from the second modulating electrical signal. The second electrical signal may have a larger voltage swing than the first electrical signal. The first electrical signal voltage swing may be 0.85 volts and the second electrical signal voltage swing may be 1.5 volts, for example. The first and second electrical signals may have different frequencies.

A semiconductor circuitry includes a first circuitry having a differential transistor pair and a pair of current sources connected in series to the differential transistor pair, a pair of transmission lines connected to the differential transistor pair at the opposite side to the current sources, and a second circuitry, connected to a node between the differential transistor pair and the current sources, and configured to test operations of at least the differential transistor pair and a latter-stage circuity connected to the transmission lines, in the state where the current outputs of the pair of current sources are stopped.

Facilitating ad hoc daisy-chaining of dynamically addressable devices having configurable physical layer interfaces together in a serial manner is presented herein. A system can include a group of devices communicatively coupled with respective devices of the group of devices in a daisy-chained manner via physical layer (PHY) interfaces of the respective devices including a group of available communication protocol configurations including a low voltage differential signaling (LVDS) based PHY configuration, a controller area network (CAN) based PHY configuration, and/or a single-ended serial communication PHY configuration including a complementary metal-oxide-semiconductor (CMOS) based interface or a transistor-transistor logic (TTL) based interface. Further, a host device of the system is directly connected, using a single-ended Manchester encoded serial communication interface, to a foremost device of the group of devices and to successive devices of the respective devices, via the foremost device, using the single-ended Manchester encoded serial communication interface.