Systems for bi-directional single-ended transmission are described. For example, a system may include a receiver with a first differential input terminal and a second differential input terminal, wherein the first differential input terminal is coupled to a first node and the second differential input terminal is coupled to a second node; a transmitter with an output terminal coupled to a third node; a first inductor connected between the first node and the third node; a second inductor connected between the second node and the third node; and a shunt resistor connected between the third node and a ground node.

A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.

A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

Methods of operating a communication node are provided. A method of operating a communication node may include transmitting a first power line communication signal from the communication node to a sensor device that is at or adjacent an electric grid device. The method may include receiving from the sensor device a second power line communication signal that is responsive to the first power line communication signal, at the communication node. Moreover, the method may include determining a distance between the communication node and the electric grid device by measuring an electrical parameter of the second power line communication signal, at the communication node. Related communication nodes are also described.

Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.

According to an embodiment, a module M1 includes an internal circuit 14, and a standard information transmitting unit 15 that transmits a result of a comparison between a voltage supplied from an externally-disposed control device 1 and a threshold voltage specified based on a communication standard of the internal circuit 14 to the control device 1 as information on the communication standard of the internal circuit 14. As a result, the module M1 can communicate with the control device 1 according to a correct communication standard.

An interconnection substrate includes: a substrate having a first surface and a second surface opposite the first surface; and a transmission line including two parallel through-hole interconnections that are exposed to the first and second surfaces and are formed inside the substrate. Also, at least one of the two through-hole interconnections includes a narrow portion having a smaller diameter than a diameter of the through-hole interconnection in the first surface and a diameter of the through-hole interconnection in the second surface.