Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

A controller area network (CAN) transmitter includes an output stage circuit including a CANH port and a CANL port, and an input stage circuit configured to receive an input signal. The input signal is configured to indicate whether the output stage circuit is to provide dominant or recessive states. The CAN transmitter includes a cascode circuit configured to provide output signals on the output stage circuit to provide dominant or recessive states based on the input signal. The CAN transmitter includes a switch circuit configured to, based upon the input signal, switch the cascode circuit on and off.

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

A single-chip integrated circuit is disclosed, wherein the single-chip integrated circuit comprises at least one unidirectional communication channel for converting a first electrical signal to a first optical signal and at least one bidirectional communication channel for converting a second electrical signal to a second optical signal and converting a third optical signal to a third electrical signal.

Systems and methods for designing, using, and/or implementing beacon-enabled communications for variable payload transfers are described. In various embodiments, these systems and methods may be applicable to power line communications (PLC). For example, a method may include implementing a superframe having a plurality of beacon slots, a plurality of intermediate slots following the beacon slots, and a poll-based Contention Free Period (CFP) slot following the intermediate slots. Each of the beacon slots and each of the intermediate slots may correspond to a respective one of a plurality of frequency subbands, and the poll-based CFP slot may correspond to a combination of the plurality of frequency subbands. The method may also include receiving a poll request over a first of the plurality of frequency subbands during the poll-based CFP slot, and then transmitting a data packet over a second of the plurality of frequency subbands during the poll-based CFP slot.

Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.

An antenna device includes: a first variable phase amplifier that outputs a first signal to a first transmission line without outputting a second signal to a second transmission line; a second variable phase amplifier that outputs a fourth signal to a fourth transmission line without outputting a third signal to a third transmission line; a phase comparator that acquires a first reflected signal that is obtained by reflecting the first signal by a first antenna element from the second transmission line, acquires a second reflected signal that is obtained by reflecting the fourth signal by a second antenna element from the third transmission line, and detects a phase difference between the first and the second antenna elements based on the first and the second reflected signals; and a phase amplitude controller that calibrates a phase between the first and the second antenna elements based on the detected phase difference.

Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

An input stage for an LVDS receiver circuit is provided, which includes at least one supply voltage connection as well as a first and a second stage input to be acted upon by a differential input signal pair. The input stage further includes a first and a second differential stage, the stage inputs being directly connected to one input each of the first differential stage and indirectly, via one level-shifting circuit each, to one input each of the second differential stage. According to the present invention, the first and the second differential stage are connected to the supply voltage connection via one transistor each of a third differential stage, the control input of one of these transistors being connected to a measuring path connecting the stage inputs to one another, with the control input of the other transistor being connected to an apparatus/device (arrangement) for providing a reference voltage.