A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

The present invention provides a transmitter including a first variable resistor, a first transistor, a second transistor, a third transistor and a fourth transistor is disclosed. The first variable resistor is coupled between a supply voltage and a first node. A first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to a first output terminal of the transmitter. A first electrode of the second transistor is coupled to the first output terminal of the transmitter, and a second electrode of the second transistor is coupled to a second node. A first electrode of the third/fourth transistor is coupled to the first node, and a second electrode of the third/fourth transistor is coupled to a second output terminal of the transmitter.

In some examples, a device includes a capacitor arranged across the galvanic isolation barrier, where the capacitor is configured to communicate a single-ended signal from a first voltage domain to a second voltage domain. The device also includes a high-pass filter arranged in the second voltage domain and configured to receive the single-ended signal from the capacitor. The device further includes a low-pass filter arranged in the second voltage domain and coupled between the high-pass filter and a low-impedance node. The high-pass filter is coupled between the capacitor, the low-pass filter, and the low-impedance node, and the low-pass filter is configured to generate a differential signal.

An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

A differential transmission line having a switch may comprise: a first transmission line comprising a first distribution element having a first impedance; a second transmission line comprising a second distribution element having a second impedance; and a first switch block connected between a first end of the first transmission line and a first end of the second transmission line, wherein the first switch block comprises a first switch connected in series to the first end of the first transmission line, a second switch connected in series to the first end of the second transmission line, a first-cross capacitor connected between a first terminal of the first switch and a second terminal of the second switch, and a second cross-capacitor connected between a first terminal of the second switch and a second terminal of the first switch.