Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.

A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. An amplifier stage coupled to the intermediate node produces an amplified rectified signal at an output node that is indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage includes a resistive element coupled between the intermediate node and the supply voltage node in parallel to the load circuit.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

A differential transmission circuit for a communication device performs bidirectional communication via a differential transmission line. The differential transmission circuit include: output transistors that are turned on and off according to a drive signal during a transmission period; a signal generation unit that generates and outputs the drive signal; short-circuit transistors connected between gates and drains of the output transistors; and a cut off unit that cuts off a supply path of the drive signal between the signal generation unit and the gates of the output transistors. The cut off unit cuts off the supply path of the drive signal during a reception period in which a reception operation is performed by the communication device.

According to one embodiment, a semiconductor integrated circuit includes first and second power supply lines, first and second nodes, and first and second circuits. The first circuit is configured to supply a first current to the second power supply line, from the first node or the second node. The second circuit is configured to supply a second current from the first power supply line to the first node based on a magnitude of the first current, and to supply a third current from the first power supply line to the second node based on the magnitude of the first current.

An electronic device and an operating method thereof are provided. The electronic device includes a receiver, a memory, a processor configured to search the memory for fixed rate link (FRL) transmission bandwidth data for a source device in response to an electrical connection to the source device, perform FRL link training with a bandwidth value of the FRL transmission bandwidth data determined according to a FRL transmission bandwidth data search result, and process a content signal transmitted with a transmission bandwidth when the FRL link training is completed, and a reproducing device configured to perform a reproducing operation based on the processed content signal.

Various embodiments relate to detecting collisions on a communication network. A method may include transmitting a first signal to a shared bus. The method may also include observing a second signal at the shared bus during the transmitting. Further, the method may include detecting a collision on the shared bus in response to an amplitude of the second signal being one of greater than a first threshold and less than a second threshold.

Circuits, methods, and apparatus that provide improved data recovery for data transmitted through a channel of limited bandwidth. An example can provide circuits, methods, and apparatus that can equalize losses in a physical channel. This equalization can provide an overall channel response that is more consistent and uniform.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.