A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

A signal transmitting device includes an output control circuit and a transmitting circuit. The output control circuit generates a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol and an inverted flag signal by inverting the logic levels of second bits of a first symbol, a second symbol, a third symbol, and a fourth symbol, and generates a first output control signal and a second output control signal based on the first to fourth encoded symbols, when the maximum transition is present among the first to fourth symbols. The transmitting circuit may transmit the inverted flag signal and a Tx (Transmit) signal generated based on the first and second output control signals.

A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

A system that incorporates teachings of the present disclosure may include, for example, an adaptive impedance matching network having an RF matching network coupled to at least one RF input port and at least one RF output port and comprising one or more controllable variable reactive elements. The RF matching network can be adapted to reduce a level of reflected power transferred from said at least one input port by varying signals applied to said controllable variable reactive elements. The one or more controllable variable reactive elements can be coupled to a circuit adapted to map one or more control signals that are output from a controller to a signal range that is compatible with said one or more controllable variable reactive elements. Additional embodiments are disclosed.

A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.

A transmission circuit including four transmission component sets for Ethernet is provided. For each of the transmission component sets, a first capacitor and a first inductor are cascaded, the first inductor is coupled to the Ethernet connector via the first transmission line (TL), the first capacitor is coupled to the Ethernet chip via the second TL; a second capacitor and a second inductor are cascaded, the second inductor is coupled to the Ethernet connector via the third TL, the second capacitor is coupled to the Ethernet chip via the fourth TL; a first component set is coupled between a first contact and a second contact, the first contact is located between the first capacitor and the first inductor, and the second contact is located between the second capacitor and the second inductor; and a second component set is coupled between the second TL and the fourth TL.

A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

A mobile device including a housing having a distal end, and electronics disposed in the housing configured to operate the mobile device. A connector is coupled to the electronics, and a Pi-shaped antenna has a coupling coupled to the connector to create a resonance using the connector. The Pi-shaped antenna and the connector are configured to wirelessly send and receive the wireless signals. An impedance matching network matches the impedance of the electronics to the Pi-shaped antenna. In some embodiments, the impedance matching network is switchable by the electronics and is configured to match an impedance of the electronics to the Pi-shaped antenna in at least two states, over multiple RF bands.

A multiplexer device includes an antenna node connected to an antenna for at least one of receiving and transmitting signals; multiple band pass filters connected to the antenna node, each band pass filter having a different passband; and multiple notch filters connected in to the antenna node and the multiple band pass filters, each notch filter having a different stopband corresponding to one of the passbands of the band pass filters. The notch filters are connected in parallel with one another in order to reduce insertion loss.

An Ethernet device having an Ethernet connector comprising first and second pairs of contacts to carry BaseT Ethernet communication signals wherein at least one of the contacts of the first pair of contacts and at least one of the contacts of the second pair of contacts are configured to conduct at least two different magnitudes of DC current flow without interfering with the BaseT Ethernet communication signals.