A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal.

A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

A signal transmitting device includes an output control circuit and a transmitting circuit. The output control circuit generates a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol and an inverted flag signal by inverting the logic levels of second bits of a first symbol, a second symbol, a third symbol, and a fourth symbol, and generates a first output control signal and a second output control signal based on the first to fourth encoded symbols, when the maximum transition is present among the first to fourth symbols. The transmitting circuit may transmit the inverted flag signal and a Tx (Transmit) signal generated based on the first and second output control signals.

Systems for bi-directional single-ended transmission are described. For example, a system may include a receiver with a first differential input terminal and a second differential input terminal, wherein the first differential input terminal is coupled to a first node and the second differential input terminal is coupled to a second node; a transmitter with an output terminal coupled to a third node; a first inductor connected between the first node and the third node; a second inductor connected between the second node and the third node; and a shunt resistor connected between the third node and a ground node.

A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

A system for transmitting control systems over twisted pair cabling. The system includes a first microcontroller transmitting a first single ended signal and receiving a second single ended signal. It also includes a first differential transmitter coupled to the first microcontroller for receiving the first single ended signal from the first microcontroller and converting it to a differential signal over a first differential line and a second differential line; and, a first differential receiver coupled to the first microcontroller for receiving a third differential line and a fourth differential line and converting it to a differential receiver signal, the differential receiver signal coupled to the second single ended signal. The system has a first transformer having first, second, third, and fourth center-tapped coils, the first differential line coupled to the center tap of the first coil, the second differential line coupled to the center tap of the fourth coil, the third differential line coupled to the center tap of the second coil, and the fourth differential line coupled to the center tap of the third coil, whereby the common mode of the first transformer is used to transmit a first control signal and to receive control signal responses over the twisted pair at the first processor.

A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal of the predetermined cycle length and the predetermined data rate; a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state; a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state; a first driver circuit configured to output a signal corresponding to a signal output from the first selector; and a second driver circuit configured to output a signal corresponding to a signal output from the second selector.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

The present application discloses a method for storing data of a transmission signal, which includes: upon the reception of the transmission signal, analyzing a clock signal corresponding to the transmission signal to obtain a signal frequency of the clock signal; according to the signal frequency, acquiring zero-volt time points of a clock signal after signal superposition with the transmission signal; acquiring a preset time length, and according to the zero-volt time points and the preset time length, generating data storage time periods with each of the zero-volt time points as a central time point; and storing data of the transmission signal within each of the data storage time periods. The present application further provides an apparatus for storing data of a transmission signal and a computer readable storage medium.