Patent classifications
H04L25/49
Wireless transceiver
Embodiments of the present disclosure disclose a wireless transceiver. The wireless transceiver includes a second control switch, and the second control switch may selectively connect a signal output end of a coupler or a signal output end of a low noise amplifier LNA to a signal input end of the down converter. Therefore, when the signal output end of the coupler is connected to the down converter, the coupler, the down converter, and the analog-to-digital converter ADC form an observer; when the second control switch connects the signal output end of the low noise amplifier LNA to the signal input end of the down converter, a transceiver antenna, the low noise amplifier LNA, the down converter, and the analog-to-digital converter ADC form a receiver. Therefore, the embodiments of the present disclosure can greatly save hardware costs of a system for implementing an observer circuit.
Edge-based communication with a plurality of slave devices
Methods, systems and devices related to bidirectional edge-based pulse width modulation communication systems are disclosed. In some implementations, upon receipt of a predetermined trigger pulse at least two slave devices perform an action.
Serial-Link Receiver Using Time-Interleaved Discrete Time Gain
A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.
PAM4 TRANSCEIVERS FOR HIGH-SPEED COMMUNICATION
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
SENSOR SIGNALING OF ABSOLUTE AND INCREMENTAL DATA
A sensor integrated circuit (IC) includes a sensing element configured to sense a parameter associated with a target, a processor coupled to the sensing element and configured to generate a sensed signal indicative of the parameter associated with the target, and an output module coupled to receive the sensed signal. The output module is configured to transmit absolute data on a message line at a first rate and transmit incremental data on one or more index lines at a second rate, wherein the second rate is faster than the first rate, wherein the incremental data comprises data associated with changes in the absolute data and wherein an edge or a pulse is used to indicate an incremental change has occurred in the absolute data.
HIGH SPEED COMMUNICATIONS SYSTEM
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
HIGH SPEED COMMUNICATIONS SYSTEM
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
METHOD FOR GATEWAY SIGNALING FOR MISO OPERATION AND APPARATUS THEREFOR
Disclosed herein are a gateway-signaling method for Multiple-Input Single-Output (MISO) operation and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a predistortion unit for performing predistortion for decorrelating signals corresponding to transmitters using the number of transmitters used for MISO and a transmitter coefficient index that are identified using a timing and management packet transmitted through a Studio-to-Transmitter Link (STL), thereby generating a pre-distorted signal; and an RF signal generation unit for generating an RF transmission signal using the pre-distorted signal corresponding to the transmitter coefficient index.
Ultra-high-speed PAM-N CMOS inverter serial link
Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.
PAM-4 DFE architectures with symbol-transition dependent DFE tap values
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.