A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.

A digital filter for filtering a pulse density modulation (PDM) signal is presented. The filter has a first filter circuit to receive an input signal and to provide a filtered input signal at successive time steps which include a first filtered value at the first time step and a second filtered value at a second time step. The filter also has a quantizer to provide an output signal comprising output values at successive time steps and a filter variable circuit with a first multiplication circuit to receive the first filter variable, and divide the first filter variable by a first gain factor and a first summing circuit configured to receive the divided first filter variable, receive the output signal, and add the divided first filter variable and the first output value and a second multiplication circuit and a delay circuit.

The present invention relates to a circuit structure for realizing real-time pre-distortion calibration of broadband IQ modulation, comprises a baseband generation module, for the calibration signal generator to generate two orthogonal sine cosine calibration signals respectively according to the calibration bandwidth and the order of the pre-distortion filter, and the data switch is switched to the relevant data channel; a digital-to-analog conversion module, for converting the signals into analog I and Q baseband signals; a frequency synthesis module, for generating signals in a certain frequency range; a IQ modulation module, for mixing the analog baseband signal with the local oscillator signal; an amplitude control module, for continuous adjustment of the RF signal power. The present invention also relates to a method for realizing real-time pre-distortion calibration processing of broadband IQ modulation. With the circuit structure and method of the present invention for realizing real-time pre-distortion calibration of broadband IQ modulation, the calibration process is completed locally in real time, solving the problem of frequency response error correction caused by hardware circuit performance change, so that automatic pre-distortion calibration of frequency response can be completed on site in real time.

The present invention relates to a circuit structure for realizing real-time pre-distortion calibration of broadband IQ modulation, comprises a baseband generation module, for the calibration signal generator to generate two orthogonal sine cosine calibration signals respectively according to the calibration bandwidth and the order of the pre-distortion filter, and the data switch is switched to the relevant data channel; a digital-to-analog conversion module, for converting the signals into analog I and Q baseband signals; a frequency synthesis module, for generating signals in a certain frequency range; a IQ modulation module, for mixing the analog baseband signal with the local oscillator signal; an amplitude control module, for continuous adjustment of the RF signal power. The present invention also relates to a method for realizing real-time pre-distortion calibration processing of broadband IQ modulation. With the circuit structure and method of the present invention for realizing real-time pre-distortion calibration of broadband IQ modulation, the calibration process is completed locally in real time, solving the problem of frequency response error correction caused by hardware circuit performance change, so that automatic pre-distortion calibration of frequency response can be completed on site in real time.

This application discloses example data encoding methods, data decoding methods, and communication apparatuses. One example data encoding method includes generating M encoding units and distributing the M encoding units to N transmission channels. The M encoding units are obtained by encoding L frames. The M encoding units include at least one first-type unit. A first-type unit of the at least one first-type unit includes a first identifier. The first identifier indicates a start location that is in the first-type unit and that is of a frame header of a first frame in the L frames. M, N, and L are integers greater than or equal to 1.

An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Edge buffers corresponding to potentially interfering analog signal lines are searched to identify potentially interfering pulse edges. A set of potentially interfering pulse edges are selected for interference mitigation, and the target signal pattern is modified to perform preemptive interference mitigation based at least in part on the selected pulse edges.

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Based at least in part on determining that edge buffers corresponding to one or more potentially interfering analog signal lines include edge data corresponding to post-target pulse edges, one or more potentially interfering signal patterns are identified. A selected set of the potentially interfering signal patterns are used to modify the target signal pattern to perform preemptive interference mitigation.