A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller. At least one of the first battery cell controller or the second battery cell controller includes at least one encoding/decoding circuit for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique, including modulating the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet including a plurality of symbols constructed and arranged with at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet includes a DC balanced line code in each of the symbols.

Utilizing a fast Fourier transform (FFT) to cancel a non-liner phase response of a digital infinite impulse response (IIR) lowpass filter is presented herein. An apparatus generates, via the digital IIR lowpass filter, respective discrete time domain orthogonal frequency-division multiplexing (OFDM) based digital output values comprising non-linear phase distortion; in response to removing respective cyclic prefix values from the respective discrete time domain OFDM based digital output values to obtain a group of discrete time domain OFDM based digital output values, generates, based on such values via a digital FFT, respective frequency domain OFDM based digital output values comprising a non-linear phase response of the digital FFT; and based on the non-linear phase response of the digital IIR lowpass filter, applies phase compensation to the respective frequency domain OFDM based digital output values to obtain frequency compensated frequency domain OFDM based digital output values comprising a linear phase response.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

In a distribution shaping method, information compression and distribution shaping are executed at the same time. A symbol sequence of a predetermined length is allocated to an input bit sequence of a predetermined length on a one-to-one basis. In the allocation, a bit sequence smaller in entropy is allocated a symbol sequence smaller in average power.

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

A first wireless device may receive, from a second wireless device, a transmission associated with an MLC scheme. The MLC scheme may include a plurality of bits with at least one first bit corresponding to a first level of the plurality of bits and at least one second bit corresponding to a second level of the plurality of bits. The at least one first bit may be coded with a first level of complexity, but the at least one second bit may be coded with either the first level of complexity or a second level of complexity, where the first level of complexity may be a higher level of complexity than the second level of complexity. The first wireless device may decode the at least one first bit and the at least one second bit using a decoder having a corresponding level of complexity.

A PAM transceiver configured to process an electrical data signal having at least three states includes an electronic circuit comprising: a data interface configured to connect to a duplex communication channel; a first circuit section connected to the data interface; and a second circuit section connected to the data interface. The first circuit section includes an equalizer for compensating for distortions in the data signal and an interpreter downstream of the equalizer for recognizing symbols. The second circuit section includes a delay unit for time-shifting the data signal and an MMA processor for recognizing a signal phase of the data signal. The first circuit section and the second circuit sections are routed to the MMA processor. The second circuit section has a finite impulse response filter configured to monotonize an impulse response of the communication channel.

A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.

A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. When transmitting a first payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and the transmitter transmits a clock training pattern and the first payload in the second mode.