Patent classifications
H04L25/49
MEMORY DEVICE, METHOD OF CALIBRATING SIGNAL LEVEL THEREOF, AND MEMORY SYSTEM HAVING THE SAME
A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.
IBOC compatible superposition modulation by independent modulators utilizing clipping noise from peak-to-average power reduction
According to an aspect of the present invention, there is provided a method for providing additional bandwidth to receivers that can decode a higher modulation comprising trading a peak-to-average power ratio (PAPR) reduction induced constellation noise of all or a subset of in-band on-channel (IBOC) carriers within an orthogonal frequency division multiplexing (ODFM) waveform with data carrying superposition modulation.
Receiver, method for detecting an error in a signal comprising a datum, method for transmitting a datum and a method for detecting an error in a signal
A receiver according to an embodiment includes a receiver circuit to receive a transition in a first direction, a second transition after the first transition in a second direction, and a third transition after the second transition in the first direction and a fourth transition in the second direction of a signal. The receiver circuit is adapted to determine a first time period between the first and third transitions and to determine a second time period between the second and fourth transitions. The receiver circuit is adapted to determine a datum based on at least one of the first time period and the second time period. Furthermore, the receiver is adapted to indicate an error, if the determined first and second time periods do not fulfil a predetermined verification relationship.
Apparatus and method for multilevel coding (MLC) with binary alphabet polar codes
A method includes receiving multiple bits to be transmitted. The method also includes applying a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The method further includes generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate. In addition, the method could include applying a second binary alphabet polar code to a second subset of the multiple bits to generate second encoded bits. The second encoded bits are associated with the second bit level. The second binary alphabet polar code is associated with a second coding rate such that the bit levels have substantially equal error rates.
Multi-level signal clock and data recovery
A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
Antenna tuning control using general purpose input/output data
A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.
Data-enable mask compression on a communication bus
An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.
Communication apparatus and digital to analog conversion circuit thereof
The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.
Communication apparatus and digital to analog conversion circuit thereof
The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.
Synchronously-switched multi-input demodulating comparator
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.