Systems, methods, and apparatus for one wire communication are disclosed. An apparatus has a line driver adapted to power one or more slave devices coupled to a one-wire serial bus, a circuit for encoding and decoding data in signals transmitted over the serial bus, and a controller. The line driver may maintain the wire at or above a voltage base level during transactions conducted over the wire. A data-encoded signal provided by the coding circuit may be transmitted on the wire in a first transaction and a data-encoded signal received from the wire may be decoded during a second transaction. The line driver may power the one or more slave devices when it maintains the wire at or above the first voltage level. The first signal and the second signal transitions within a voltage range defined by the first voltage level and a second voltage level.

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Methods, systems and devices for reducing pattern effects in pulse amplitude modulation (PAM) signals in semiconductor optical amplifiers (SOAs) are described. One method for digital communication includes generating, based on (2M+1) N-level PAM (PAM-N) symbols, an index corresponding to an entry of a look-up table (LUT) that comprises adjustment values, wherein M and N are integers, determining, based on the index, a selected adjustment value from the LUT, generating a pre-distorted PAM-N symbol based on a difference between a center symbol of the (2M+1) PAM-N symbols and the selected adjustment value, and generating, using an SOA, a waveform that includes the pre-distorted PAM-N symbol.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.

It is described a modulator apparatus (3) comprising: an input terminal (23) structured to receive an analog electrical signal (x(t)) having an information content to be transmitted; a loop filter structured to receive an error signal ((t) and provide a filtered signal (s(t)), the loop filter being configured to minimize said error signal ((t)); a modulator device (10) configured to module the filtered signal (s(t)) and provide a Pulse Width Modulated, PWM, signal (y(t)) to be transmitted including a plurality of pulses having corresponding widths correlated to non-quantized amplitudes of the filtered signal (s(t)); a first pulse width demodulator (11) configured to receive the PWM, signal (y(t)) and provide a demodulated signal ((t)) and a difference module (12) configured to receive the analog electrical signal (x(t)) and the demodulated signal ((t)) and provide the error signal ((t)).

Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values. Such an apparatus has been found to provide a low power technique for a receiver, whilst still enabling the improved sensitivity benefits of using soft decisions to be achieved, and allows the apparatus to be constructed using all digital components.

A galvanic isolation circuit comprising: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connectable to a first transceiver a second communication link connected to the second side of the galvanic isolator and connectable to a second transceiver; a first reference terminal connectable to the first transceiver; a second reference terminal connectable to the second transceiver; and an AC short capacitor connected between the first reference terminal and the second reference terminal.