This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

According to one embodiment, a semiconductor integrated circuit includes: a converter configured to convert an analog signal into a digital signal based on a clock signal; a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal; a recovery circuit configured to recover the clock signal; and a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.

A device for controlling spectral regrowth includes a transmission signal processor configured to generate a baseband transmission signal and a controller. The controller is configured to adjust delay of an envelope tracking path that provides a supply voltage to an envelope tracking power amplifier included in a transmission path that generates a radio frequency (RF) transmission signal from the baseband transmission signal. The controller may obtain allocation information of resource blocks included in the RF transmission signal from the transmission signal processor and may determine the delay of the envelope tracking path based on the allocation information.

A communication device, method, and data transmission system are provided. An illustrative method is disclosed to include at least one data port and lossless IPG circuitry that operates on the transmit-side and/or receive-side of the data transmission system. The lossless IPG circuitry may include a lossless IPG insertion circuit and/or a lossless IPG removal circuit that work in cooperation with each other to ensure that data streams do not violate any predefined communication protocols or requirements thereof.

A communication device, method, and data transmission system are provided. An illustrative method is disclosed to include at least one data port and lossless IPG circuitry that operates on the transmit-side and/or receive-side of the data transmission system. The lossless IPG circuitry may include a lossless IPG insertion circuit and/or a lossless IPG removal circuit that work in cooperation with each other to ensure that data streams do not violate any predefined communication protocols or requirements thereof.

A single-ended inter-chip data transmission system and a single-ended inter-chip data reception system are provided for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus.

The present disclosure relates to a bus device and a corresponding bus system. Furthermore, the present disclosure relates to a corresponding method of operating a bus device. In accordance with a first aspect of the present disclosure there is provided a bus device comprising a bus protocol controller with a transmit data output and a bus transceiver with a transmit data input coupled to the transmit data output of the bus protocol controller, wherein the bus protocol controller is configured to provide a serial bit stream designated for transmission through a bus via the transmit data output of the bus controller and via the transmit data input to the bus transceiver and to provide a switching signal within the serial bit stream, and wherein the bus transceiver is configured to switch between different operating modes in response to the switching signal.

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.

Systems, methods, and apparatus for one wire communication are disclosed. An apparatus has a line driver adapted to power one or more slave devices coupled to a one-wire serial bus, a circuit for encoding and decoding data in signals transmitted over the serial bus, and a controller. The line driver may maintain the wire at or above a voltage base level during transactions conducted over the wire. A data-encoded signal provided by the coding circuit may be transmitted on the wire in a first transaction and a data-encoded signal received from the wire may be decoded during a second transaction. The line driver may power the one or more slave devices when it maintains the wire at or above the first voltage level. The first signal and the second signal transitions within a voltage range defined by the first voltage level and a second voltage level.