An automotive Ethernet physical-layer (PHY) transceiver includes an analog Front End (FE) and a digital processor. The FE is configured to receive an analog Ethernet signal over a physical Ethernet link while the Ethernet PHY transceiver is operating in a vehicle, and to convert the received analog Ethernet signal into a digital signal. The digital processor is configured to hold one or more noise profiles that characterize respective predefined noise types of noise signals that are expected to corrupt the received analog Ethernet signal, to classify an actual noise signal present in the digital signal into one of the noise types, using the noise profiles, and in response to deciding that the actual noise signal matches a given noise type among the predefined noise types, to apply a noise mitigation operation selected responsively to the given noise type.

A fail-safe interface for a by-wire vehicle control system merges driver commands and external commands developed by a by-wire control unit to form a failure-tolerant actuator command that never diminishes a driver command. External commands are passed through a fault detection circuit that filters out aberrant cyclical and constant command signals from the by-wire control unit, and the actuator command is determined according to the higher or maximum of the driver-generated and external commands. The interface is powered by vehicle power supply, and is electro-optically isolated from the external control unit so that if the external control unit loses power, the actuator command faithfully follows the driver command.

A fail-safe interface for a by-wire vehicle control system merges driver commands and external commands developed by a by-wire control unit to form a failure-tolerant actuator command that never diminishes a driver command. External commands are passed through a fault detection circuit that filters out aberrant cyclical and constant command signals from the by-wire control unit, and the actuator command is determined according to the higher or maximum of the driver-generated and external commands. The interface is powered by vehicle power supply, and is electro-optically isolated from the external control unit so that if the external control unit loses power, the actuator command faithfully follows the driver command.

Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.

A receiving apparatus that receives a signal modulated by a frequency modulation scheme, using a plurality of receiving antennas includes an FSK modulation-compatible interference extraction unit that extracts, from a plurality of reception signals received by the plurality of receiving antennas, interference signals that are frequency components other than frequency components of desired signals at which power is concentrated, a complex weight calculator that calculates a complex weight of each reception signal, on the basis of the same number of the interference signals as the number of the receiving antennas, and a complex weight multiplication and combining unit that multiplies each of the plurality of reception signals by the corresponding complex weight, and combines the reception signals that have been multiplied by the complex weights.

A method for transmitting a demodulation reference signal and a network device are provided. The method includes: determining whether to configure a corresponding demodulation reference signal (DMRS) for a shared channel, according to a mapping type of the shared channel, the number of symbols transmitted on the shared channel, and the number of DMRS symbols; configuring a target number of DMRSs for the shared channel, when determining to configure the corresponding DMRS for the shared channel; and mapping the target number of DMRSs onto a target transmission resource for transmission.

A method for transmitting a demodulation reference signal and a network device are provided. The method includes: determining whether to configure a corresponding demodulation reference signal (DMRS) for a shared channel, according to a mapping type of the shared channel, the number of symbols transmitted on the shared channel, and the number of DMRS symbols; configuring a target number of DMRSs for the shared channel, when determining to configure the corresponding DMRS for the shared channel; and mapping the target number of DMRSs onto a target transmission resource for transmission.

A system and a method of demodulating a frequency shift keying signal are provided. The method includes steps of: inputting the frequency shift keying signal; accumulating cycles of the frequency shift keying signal to a reference cycle number from a time point; finding an initial point of each of pulse waves of the frequency shift keying signal; accumulating the cycles to the reference cycle number multiple times from the initial point and extracting data of each accumulation; determining whether or not the number of times of extracting the data reaches a preset value, if not, returning to the previous step, if yes, performing the next step; determining whether or not a difference between the data is larger than a threshold, if not, outputting a first bit value, if yes, outputting a second bit value; and packing the first and second bit values into a demodulated signal.

A system and a method of demodulating a frequency shift keying signal are provided. The method includes steps of: inputting the frequency shift keying signal; accumulating cycles of the frequency shift keying signal to a reference cycle number from a time point; finding an initial point of each of pulse waves of the frequency shift keying signal; accumulating the cycles to the reference cycle number multiple times from the initial point and extracting data of each accumulation; determining whether or not the number of times of extracting the data reaches a preset value, if not, returning to the previous step, if yes, performing the next step; determining whether or not a difference between the data is larger than a threshold, if not, outputting a first bit value, if yes, outputting a second bit value; and packing the first and second bit values into a demodulated signal.

A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively holds or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.