The present technology relates to a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction. The present technology can be applied to a backside-illumination CMOS image sensor, for example.

The present technology relates to a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction. The present technology can be applied to a backside-illumination CMOS image sensor, for example.

An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

A high dynamic range imaging pixel may include first and second photodiodes that generate charge in response to incident light. The second photodiode may have a higher sensitivity than the first photodiode. When generated charge in the first photodiode exceeds a given charge level, the charge may overflow through a transistor to a capacitor. The overflow path from the first photodiode to the capacitor may optionally pass through the floating diffusion region. A transistor may be coupled between the first and second photodiodes. A gain select transistor may be coupled between the floating diffusion region and the capacitor. After sampling the overflow charge, the charge from both the first and second photodiodes may be sampled. In one arrangement, overflow charge may be transferred to a capacitor in a subsequent row.

Designs of an anti-blooming sensing element or simply sensor are described. According to one aspect of the designs, each sensing element includes a photosensor, a pair of first and second circuits, a store device and a readout circuit. The first and second circuits, sandwiching the photosensor from a circuit perspective, are mirrored and balanced in impedance. The first circuit provides an inherent mechanism to discharge excessive charge accumulated on the photosensor before a predefined exposure time ends. Each of the two circuits includes two transistors.

The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

An imaging device includes an image pickup device having pixels and a correction processing unit that corrects signals output from the image pickup device, the pixels include a visible light pixel that receives light corresponding to a visible light wavelength range and an infrared light pixel that is arranged adjacent to the visible light pixel and receives light corresponding to an infrared wavelength range, and the correction processing unit includes a calculation unit that performs a first process of reducing, from a signal of the infrared light pixel, a component in the pixel signal of the infrared light pixel and based on an inflow amount of charges to the infrared light pixel from another pixel adjacent to the infrared light pixel and a second process of obtaining a signal corresponding to a difference between pixel signals of the visible light pixel and the infrared light pixel after the first process.

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.