A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

An image sensor may include an array of dual conversion gain image pixels arranged in rows and columns. The image pixels arranged along the same column may be coupled to a column line. The column line may be coupled to anti-eclipse control circuitry. In one suitable arrangement, the anti-eclipse control circuitry may include a comparator that compares the output signal on the column line to an anti-eclipse bias voltage. If, during a reset sampling period, the output signal on the column line is less than the anti-eclipse bias voltage, a current source may be used to charge the bottom plate of a dual conversion gate capacitor in the selected image pixel to help restore the voltage of the floating diffusion node in the selected pixel.

An imaging pixel to mitigate cross-talk effects comprises a voltage supply node to receive a supply voltage, and an output node to provide a pixel output signal. The imaging pixel further comprises a photosensitive element, and a source follower transistor having a control node coupled to the photosensitive element. The source follower transistor is interposed between the voltage supply node and the output node. The imaging pixel comprises a clamping circuit being interposed between the voltage supply node and the output node.

A light detecting device includes: one or more switch transistors, a first pixel including a first floating diffusion region coupled to a first photoelectric converter through a first transfer transistor, and a first amplification transistor coupled to the first floating diffusion region, a second pixel including a second floating diffusion region coupled to a second photoelectric converter through a second transfer transistor, and a second amplification transistor coupled to the second floating diffusion region, and a third pixel including a third floating diffusion region coupled to a third photoelectric converter through a third transfer transistor, and a third amplification transistor coupled to the third floating diffusion region. A pixel signal is differentially amplified by the first and third amplification transistors. The first and second floating diffusion regions are selectively connected to each other via one of the one or more switch transistors.

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuity is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.

A system and method for correcting oversaturated pixels in far-infrared (FIR) images captured by a shutterless FIR camera. The method includes identifying oversaturated pixels based on a pixel value analysis of an input image; creating an oversaturated pixel mask of the input image, where the oversaturated pixel mask includes the identified oversaturated pixels and excludes pixels not identified as oversaturated pixels; and correcting the oversaturated pixels of the current image using the oversaturated pixel mask, based on a scene-based nonuniformity correction (SBNC).

The present technology relates to a solid-state imaging device and an electronic device that enable a reduction in the voltage of an AD conversion circuit. A solid-state imaging device includes: a plurality of pixels; a vertical signal line configured to output a pixel signal of the pixel; and a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage. The clipping circuit includes a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor. The present technology can be applied to a CMOS image sensor, for example.

A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges accumulated in the photodiode to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a SF gate terminal and provide an amplified signal to a source follower source terminal. A row select transistor is coupled to receive the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor controlled by a bitline enable voltage is coupled to link between the bitline and a bitline source node. The bitline is coupled to an idle voltage generator, a blacksun voltage generator, and a clamp voltage generator. These three voltage generators are each constructed out of a plurality of modified dummy pixels based on the dummy pixels in the dummy rows of an image sensor pixel array.

To improve the image quality in a solid-state imaging element that performs CDS processing.

The solid-state imaging element includes an amplitude detection unit and a black spot prevention unit. The amplitude detection unit detects whether an output voltage that is a voltage of a vertical signal line for transmitting either a reset level at which a pixel is initialized or a signal level corresponding to an amount of light exceeds a predetermined determination threshold. The black spot prevention unit controls, when the output voltage exceeds the determination threshold, a first digital signal obtained by converting the reset level and a second digital signal obtained by converting the signal level to different values.

To improve the image quality in a solid-state imaging element that performs CDS processing.

The solid-state imaging element includes an amplitude detection unit and a black spot prevention unit. The amplitude detection unit detects whether an output voltage that is a voltage of a vertical signal line for transmitting either a reset level at which a pixel is initialized or a signal level corresponding to an amount of light exceeds a predetermined determination threshold. The black spot prevention unit controls, when the output voltage exceeds the determination threshold, a first digital signal obtained by converting the reset level and a second digital signal obtained by converting the signal level to different values.