An imaging device having first and second pixels is described. The first pixel includes a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The second pixel includes a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor.

An imaging device having first and second pixels is described. The first pixel includes a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The second pixel includes a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor.

The invention relates to a TDI line detector (1), comprising n TDI lines (Z1-Zn), wherein each TDI line (Z) has m pixels (P), and at least one read-out electronics (11-14), wherein the TDI line detector (1) is subdivided into x submodules (S1-S4), wherein the number of lines (Z) of a submodule (S1-S4) is n/x, wherein a discrete read-out electronics (11-14) is associated with the last line of each submodule (S1-S4), wherein the length (L1) of the read-out electronics (11-14) corresponds to an integer multiple of the length (L2) of a pixel (P), wherein x≥2 is, wherein the associated pixels (P) of different submodules (S1-S4) are arranged pixel to pixel relative to one another or the submodules (S1-S4) or groups of submodules (S1-S4) are laterally interlinked alternately by half a pixel (P).

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

Read electrodes are provided to drain signal charge of pixels from photoelectric conversion units provided in the pixels separately to a vertical transfer unit. During a first exposure period during which an object is illuminated with infrared light, signal charge obtained from a first pixel, and signal charge obtained from a second pixel adjacent to the first pixel, are added together in the vertical transfer unit to produce first signal charge. During a second exposure period during which the object is not illuminated with infrared light, signal charge obtained from the first pixel, and signal charge obtained from the second pixel adjacent to the first pixel, are transferred without being added to the first signal charge in the vertical transfer unit, and are added together in another packet to produce second signal charge.

Image capturing systems with interline CCD structures designed to reduce the delay between captures of subsequent image frames are disclosed. Proposed interline CCD structures include two or more sets of storage units associated with a given set of photodetecting elements, where each photodetecting element is associated with one storage unit of each set of storage units in that the charge generated by the photodetecting element during the acquisition of a particular image frame (i.e. during a particular exposure period) may be stored any one of these storage units prior to read-out. Providing multiple sets of storage units allows read-out of charge corresponding to one image frame and stored in one set of storage units while accumulating charge corresponding to another image frame in another set of storage units, thus reducing the delay between captures of different image frames. Consequently, errors and artifacts of the image capturing system can be minimized.

An image sensor, comprising a pixel region in which a plurality of pixel units are arranged, each pixel unit having first and second photoelectric conversion portions, a first output portion that outputs, outside of the image sensor, a first signal based on a signal from the first photoelectric conversion portion of the pixel units, and a second output portion that outputs a second signal based on a signal from the first photoelectric conversion portion and a signal from the second photoelectric conversion portion of the pixel units, wherein output of the first signal from the first output portion and output of the second signal from the second output portion are performed in parallel.

A solid-state imaging device includes a photoelectric conversion unit, a light shielding unit and a transfer transistor. The photoelectric conversion unit generates charges by photoelectrically converting light. The light shielding unit is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit. The transfer transistor transfers charges generated in the photoelectric conversion unit. During a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor. During a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

A solid-state image sensor has a pixel array and a processor configured to process a signal from the pixel array, the pixel array including a light-receiving pixel having first and second photoelectric converters and a light-shielded pixel having third and fourth photoelectric converters. The processor outputs (a) a pixel signal corresponding to charges of the first photoelectric converter, (b) an added pixel signal corresponding to a sum of charges of the first photoelectric converter and charges of the second photoelectric converter, and (c) an added reference signal corresponding to a sum of charges of the third photoelectric converter and charges of the fourth photoelectric converter, and does not output (d) a reference signal corresponding to charges of the third photoelectric converter and a reference signal corresponding to charges of the fourth photoelectric converter.

A monocentric lens-based multi-scale imaging system is disclosed. Embodiments of the present invention comprise a monocentric lens as an objective lens that collects light from a scene. Monocentric lenses in accordance with the present invention include a spherical central lens element and a plurality of lens shell sections that collectively reduce at least one of spherical and chromatic aberration from the magnitude introduced by the spherical lens element itself. A plurality of secondary lenses image the scene through the objective lens and further reduce the magnitude of aberrations introduced by the objective lens. A plurality of sensor arrays converts optical sub-images of the scene into a plurality of digital images, which can then be used to form a composite image of the scene.