A CCD photodetector and an associated method for operation. A CCD photodetector for LIDAR systems is described, including a shift register including a plurality of consecutively situated register cells, including a first register cell and a last register cell, a loading line for loading the shift register, and a read-out amplifier for unloading the shift register, the loading line and the read-out amplifier each being connected to the first register cell. A corresponding method for operating a CCD photodetector is also described.

A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal ϕ1 is applied. The second transfer gate electrodes are such that the respective second transfer gate electrodes are placed in a charge transfer unit to correspond to the single light receiving sections, and a control signal ϕ2 that differs in phase from the control signal ϕ1 for transferring plural charges is applied. The respective fixed gate electrodes are such that the respective fixed gate electrodes are placed between the first and the second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a fixed voltage is applied.

Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.

A solid-state imaging device according to an embodiment includes a photoelectric conversion unit, a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit, a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit, a second charge modulation unit, a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period, a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit, and a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit, in which, in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit.

A solid-state imaging device according to an embodiment includes a photoelectric conversion unit, a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit, a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit, a second charge modulation unit, a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period, a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit, and a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit, in which, in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit.

A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational circuits—in some embodiments, matching the size of the pixel array—is distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, thus alleviating the significant high-speed performance constraints placed on modern image sensors.

Examples of an apparatus are disclosed. In some example, an apparatus may include an array of digital pixel cells, each digital pixel cell including a photodiode and a memory device to store a digital output generated based on charge generated by the photodiode in an exposure period. The apparatus may also include an image processor configured to: receive first digital outputs from the memory devices of a first set of digital pixel cells of the array of digital pixel cells; determine, from the first set of digital pixel cells, a second set of digital pixel cells of which the first digital outputs satisfy one or more pre-determined conditions; identify, based on the second set of digital pixel cells, a third set of digital pixel cells; receive the second digital outputs generated by the third set of digital pixel cells; and perform image processing operations based on the second digital outputs.

Examples of an apparatus are disclosed. In some example, an apparatus may include an array of digital pixel cells, each digital pixel cell including a photodiode and a memory device to store a digital output generated based on charge generated by the photodiode in an exposure period. The apparatus may also include an image processor configured to: receive first digital outputs from the memory devices of a first set of digital pixel cells of the array of digital pixel cells; determine, from the first set of digital pixel cells, a second set of digital pixel cells of which the first digital outputs satisfy one or more pre-determined conditions; identify, based on the second set of digital pixel cells, a third set of digital pixel cells; receive the second digital outputs generated by the third set of digital pixel cells; and perform image processing operations based on the second digital outputs.

An imaging device having first and second pixels is described. The first pixel includes a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The second pixel includes a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor.

An imaging device having first and second pixels is described. The first pixel includes a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The second pixel includes a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor.