A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational circuitsin some embodiments, matching the size of the pixel arrayis distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, for at least many pixel-level image processing operations, thus alleviating the significant high-speed performance constraints placed on modern image sensors.

First and second images of a semiconductor die or portion thereof are generated. Generating each image includes performing a respective instance of time-domain integration (TDI) along a plurality of pixel columns in an imaging sensor, while illuminating the imaging sensor with light scattered from the semiconductor die or portion thereof. The plurality of pixel columns comprises pairs of pixel columns in which the pixel columns are separated by respective channel stops. While performing a first instance of TDI to generate the first image, a first bias is applied to electrically conductive contacts of the channel stops. While performing a second instance of TDI to generate the second image, a second bias is applied to the electrically conductive contacts of the channel stops. Defects in the semiconductor die or portion thereof are identified using the first and second images.

Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.

An image sensing device includes a pixel array including a plurality of pixels arranged in rows and columns, and suitable for outputting a plurality of pixel signals, and a plurality of readout circuits coupled to the pixel array, and suitable for compensating for readout deviations among the plurality of pixel signals when reading out the plurality of pixel signals.

Examples of an apparatus are disclosed. In some example, an apparatus may include an array of digital pixel cells, each digital pixel cell including a photodiode and a memory device to store a digital output generated based on charge generated by the photodiode in an exposure period. The apparatus may also include an image processor configured to: receive first digital outputs from the memory devices of a first set of digital pixel cells of the array of digital pixel cells; determine, from the first set of digital pixel cells, a second set of digital pixel cells of which the first digital outputs satisfy one or more pre-determined conditions; identify, based on the second set of digital pixel cells, a third set of digital pixel cells; receive the second digital outputs generated by the third set of digital pixel cells; and perform image processing operations based on the second digital outputs.

The application provides a cross-row time delay integral method, apparatus and camera. The method includes obtaining a first stage integral energy in an i-th target region from an i-th row of a first integral piece domain; transferring the first stage integral energy across rows to an i-th row of a second integral piece domain; obtaining the first stage integral energy and an second stage integral energy accumulated in the i-th target region from the i-th row of the second integral piece domain, after an integration period; outputting an image of the i-th target region containing the first stage integral energy and the second stage integral energy. The application performs cross-row integration through the energy obtained by imaging, the shooting of the target can be carried out in a higher-speed environment, the method can be implemented on the existing photoelectric device, and the method has excellent imaging quality and wide applicability.

A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational 0 in some embodiments, matching the size of the pixel arrayis distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, for at least many pixel-level image processing operations, thus alleviating the significant high-speed performance constraints placed on modern image sensors.

An image sensor, comprising a pixel region in which a plurality of pixel units are arranged, each pixel unit having first and second photoelectric conversion portions, a first output portion that outputs, outside of the image sensor, a first signal based on a signal from the first photoelectric conversion portion of the pixel units, and a second output portion that outputs a second signal based on a signal from the first photoelectric conversion portion and a signal from the second photoelectric conversion portion of the pixel units, wherein output of the first signal from the first output portion and output of the second signal from the second output portion are performed in parallel.

A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.