H04N25/72

Dual-Column-Parallel CCD Sensor And Inspection Systems Using A Sensor

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

IMAGE SENSOR

A CCD image sensor of the type for providing charge multiplication by impact ionisation has an image area and a plurality of pixels. A separate multiplication register has a plurality of multiplication elements arranged to receive charge from the pixels of the image area. Each multiplication element comprises a sequence of electrodes operable to cause multiplication, the electrodes of each multiplication element being adjacent one another and non-overlapping. The non-overlapping arrangement may be manufactured by a CMOS process thereby providing a CCD image sensor with the advantages of CCD multiplication but using a CMOS manufacturing process.

Dual-column-parallel CCD sensor and inspection systems using a sensor

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

Time delay and integration (TDI) imaging sensor and method

According to one aspect, embodiments herein provide a TDI sensor comprising a plurality of light sensing elements arranged in a row, each configured to accumulate charge proportional to an intensity of light incident on it from a field of view, and means for improving the sampling resolution of the TDI sensor by electronically introducing phase shift between a first set of image data generated by the plurality of light sensing elements at a first phase and a second set of image data generated by the plurality of light sensing elements at a second phase, for reading out the first set of image data and the second set of image data from a light sensing element at an end of the row of light sensing elements, and for generating an image of the field of view based on the two sets of phase shifted image data.

Method and apparatus for correcting smear artifacts
20180376085 · 2018-12-27 ·

1. Method and device for correcting readout smear artifacts.

2.1. Known methods for correcting smear artifacts that occur when reading out CCD sensors require considerable computing time; their implementation is cumbersome. The new method should enable more simple and efficient implementations.

2.2 In order to enable an efficient calculation of a corrected image, the readout image values and the correction values to be used are first transformed with a suitable transformation into a frequency range in which the transformed image values are then corrected by means of the transformed correction values through use of a folding operation. The folding can then be calculated in parallel. Furthermore, a method for approximately calculating corrections for an aperiodic readout smear is provided. Different efficient implementations in hardware are introduced.

2.3 Based on their efficiency, the method and the device are suitable in particular for scientific sensors that require high fill factors of the pixels but also for image sensors that are used in smartphones.

Power-Conserving Clocking for Scanning Sensors
20180091751 · 2018-03-29 ·

A time delay and integration charge coupled device includes an array of pixels and a clock generator. The array of pixels is distributed in a scan direction and a line direction perpendicular to the scan direction in which at least some of the pixels of the array include three or more gates aligned in the scan direction. The clock generator provides clocking signals to transfer charge along the scan direction between two or more pixel groups including two or more pixels adjacent in the scan direction. The clocking signals include phase signals to transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to the velocity of the target by driving the gates of the two or more pixel groups and generating a common potential well per pixel group for containing charge generated in response to incident illumination.

IMAGE SIGNAL PROCESSOR AND IMAGING SYSTEM INCLUDING THE SAME
20250024171 · 2025-01-16 · ·

An imaging system includes a frame memory component configured to perform a read operation or a write operation of image data. The imaging system also includes an image signal processor configured to write the image data input into the frame memory component in a predetermined order, process data read from the frame memory component, and output the processed image data. The image signal processor converts an order of processing the image data to a direction different from a direction in which the image data is input, process the resultant data, aligns the order of the processed image data in the predetermined order, and outputs the resultant data.

IMAGE SIGNAL PROCESSOR AND IMAGING SYSTEM INCLUDING THE SAME
20250024171 · 2025-01-16 · ·

An imaging system includes a frame memory component configured to perform a read operation or a write operation of image data. The imaging system also includes an image signal processor configured to write the image data input into the frame memory component in a predetermined order, process data read from the frame memory component, and output the processed image data. The image signal processor converts an order of processing the image data to a direction different from a direction in which the image data is input, process the resultant data, aligns the order of the processed image data in the predetermined order, and outputs the resultant data.

TIME DELAY AND INTEGRATION (TDI) IMAGING SENSOR AND METHOD
20170310918 · 2017-10-26 ·

According to one aspect, embodiments herein provide a TDI sensor comprising a plurality of light sensing elements arranged in a row, each configured to accumulate charge proportional to an intensity of light incident on it from a field of view, and means for improving the sampling resolution of the TDI sensor by electronically introducing phase shift between a first set of image data generated by the plurality of light sensing elements at a first phase and a second set of image data generated by the plurality of light sensing elements at a second phase, for reading out the first set of image data and the second set of image data from a light sensing element at an end of the row of light sensing elements, and for generating an image of the field of view based on the two sets of phase shifted image data.

Time delay and integration (TDI) imaging sensor and method

According to one aspect, embodiments herein provide a TDI image sensor comprising an array of light sensing elements, at least one clock, and an image processor, wherein the at least one clock is configured to operate a first plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a first phase and to operate a second plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a second phase, and wherein the image processor is configured to read out a first signal from the first plurality of light sensing elements corresponding to a total charge accumulated at the first phase, to read out a second signal from the second plurality of light sensing elements corresponding to a total charge accumulated at the second phase, and to combine the first signal and the second signal to generate an image.