Provided are a pixel array and an image sensor including the same. The pixel array includes a plurality of sub-pixels adjacent to each other and a readout circuit connected to the plurality of sub-pixels through a floating diffusion node. Each of the sub-pixels includes a photoelectric conversion element, an overflow transistor connected to the photoelectric conversion element, a phototransistor connected to the photoelectric conversion element and the overflow transistor, and a storage element connected to the phototransistor.

Provided are a pixel array and an image sensor including the same. The pixel array includes a plurality of sub-pixels adjacent to each other and a readout circuit connected to the plurality of sub-pixels through a floating diffusion node. Each of the sub-pixels includes a photoelectric conversion element, an overflow transistor connected to the photoelectric conversion element, a phototransistor connected to the photoelectric conversion element and the overflow transistor, and a storage element connected to the phototransistor.

In one example, an imaging device including a plurality of pixel circuits, a first control line, a second control line, a first voltage supply line, a second voltage supply line, a first light-receiving element, and a diagnosis unit is disclosed. The pixel circuits each include a first terminal, a second terminal, a third terminal, an accumulation unit, a first transistor, a second transistor, and an output unit. The first transistor is couples the third terminal to the accumulation unit on the basis of a voltage of the first terminal. The second transistor supplies a predetermined voltage to the accumulation unit on the basis of a voltage of the second terminal. The output unit outputs a signal corresponding to a voltage in the accumulation unit.

In one example, an imaging device including a plurality of pixel circuits, a first control line, a second control line, a first voltage supply line, a second voltage supply line, a first light-receiving element, and a diagnosis unit is disclosed. The pixel circuits each include a first terminal, a second terminal, a third terminal, an accumulation unit, a first transistor, a second transistor, and an output unit. The first transistor is couples the third terminal to the accumulation unit on the basis of a voltage of the first terminal. The second transistor supplies a predetermined voltage to the accumulation unit on the basis of a voltage of the second terminal. The output unit outputs a signal corresponding to a voltage in the accumulation unit.

An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

A signal processing device according to the present technology includes a multistage-branching-wired-line unit that supplies the same signal to a plurality of target elements via multistage-branched wired lines, and a logic circuit arranged at each of stages of the multistage-branching-wired-line unit, in which the wired lines in at least a certain space between the stages in the multistage-branching-wired-line unit cross each other.

An event-driven sensor including: a pixel array; a column readout circuit coupled to column output lines of the pixel array, the column readout circuit including a plurality of column register cells; and a row readout circuit including a readout memory having a storage location corresponding to each pixel of the pixel array, the readout memory having sets of one or more row lines for writing to rows of memory locations of the readout memory, wherein each row output line of the pixel array is coupled, via a corresponding row line control circuit, to a corresponding one of the sets of one or more row lines of the readout memory.

An event-driven sensor including: a pixel array; a column readout circuit coupled to column output lines of the pixel array, the column readout circuit comprising a plurality of groups of column register cells coupled in series with each other to propagate a first flag signal, wherein each column register cell is configured to activate a column event output signal when it receives the first flag signal while the detection of an event is indicated on the column output line; and a first bypassing circuit for each group of column register cells, the first bypassing circuits being coupled in series with each other to propagate the first flag signal.

An image sensor may include an array of image sensor pixels. The array of image sensor pixels may be controlled by row driver circuitry. The row driver circuitry may include row drivers that receive power supply signals from transconductance amplifier circuitry. The transconductance amplifier circuitry may include multiple amplifiers with output ports shorted to one another. Each amplifier may include input transistors, cross-coupled transistors with a low threshold voltage, and additional transistors coupled in series with the cross-coupled transistors and having a moderate or high threshold voltage.

An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.