Patent classifications
H04N25/74
Image sensor with voltage supply grid clamping
An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
Imaging device with image encryption
An imaging device includes an image sensing device, a private key generation unit, and an image encryption unit. The image sensing device includes an image generator configured to generate image data acquired by capturing as image, and a physical unclonable function (PUF) generator configured to generate physical unclonable function (PUF) data including information about at least one fixed pattern noise (FPN) data value and at least one random telegraph noise (RTN) data value. The private key (KEY) generation unit generates a private key based on the at least one FPN data value and the at least one RTN data value that are acquired from the PUF data. The image encryption unit encrypts the image data using the private key. A first transistor included in the PUF generator exhibits different properties from a second transistor that is included in the image generator and corresponds to the first transistor.
Imaging device with image encryption
An imaging device includes an image sensing device, a private key generation unit, and an image encryption unit. The image sensing device includes an image generator configured to generate image data acquired by capturing as image, and a physical unclonable function (PUF) generator configured to generate physical unclonable function (PUF) data including information about at least one fixed pattern noise (FPN) data value and at least one random telegraph noise (RTN) data value. The private key (KEY) generation unit generates a private key based on the at least one FPN data value and the at least one RTN data value that are acquired from the PUF data. The image encryption unit encrypts the image data using the private key. A first transistor included in the PUF generator exhibits different properties from a second transistor that is included in the image generator and corresponds to the first transistor.
DUAL-PROGRESSION PIXEL READOUT
Row-by-row pixel read-out is executed concurrently within respective clusters of pixels of a pixel array, alternating the between descending and ascending progressions in the intra-cluster row readout sequence to reduce temporal skew between neighboring pixel rows in adjacent clusters.
Solid-state imaging device
To improve the image quality of image data in a solid-state imaging device that reads a signal according to a potential difference between respective floating diffusion regions of a pair of pixels. A pixel unit is provided with a plurality of rows each including a plurality of pixels. A readout row selection unit selects any of the plurality of rows as a readout row every time a predetermined period elapses, and causes each of the plurality of pixels in the readout row to generate a signal potential according to a received light amount. A reference row selection unit selects a row different from a previous row from among the plurality of rows as a current reference row every time the predetermined period elapses, and causes each of the plurality of pixels in the reference row to generate a predetermined reference potential. A readout circuit unit reads a voltage signal according to a difference between the signal potential and the reference potential.
IMAGE PROCESSING DEVICE FOR CONTROLLING PIXEL OUTPUT LEVEL AND OPERATING METHOD THEREOF
An image sensor includes a pixel array that includes a first pixel group located in a first row and including a first select transistor and a first floating diffusion region, a second pixel group located in a second row and including a second select transistor and a second floating diffusion region, and a column line connected to both the first pixel group and the second pixel group. While charges generated by a photoelectric conversion element of the first pixel group are transferred to the first floating diffusion region, the first select transistor is turned off, the second select transistor is turned on, and a first voltage is applied to the column line through the second select transistor. A photoelectric conversion element of the second pixel group generates charges prior to the photoelectric conversion element of the first pixel group, so as to be transferred to the second floating diffusion region.
Signal processing device and method, and program
The present technology relates to a signal processing device and method, and a program that enable easier and more accurate failure detection. The signal processing device includes: an addition unit that adds test data for failure detection to valid data on which predetermined processing is to be performed, two or more samples processed in parallel in different paths having a same sample value in the test data; and a signal processing unit that performs the predetermined processing on the valid data and the test data that has been added to the valid data by a plurality of the paths. The present technology can be applied to in-car cameras.
Signal processing device and method, and program
The present technology relates to a signal processing device and method, and a program that enable easier and more accurate failure detection. The signal processing device includes: an addition unit that adds test data for failure detection to valid data on which predetermined processing is to be performed, two or more samples processed in parallel in different paths having a same sample value in the test data; and a signal processing unit that performs the predetermined processing on the valid data and the test data that has been added to the valid data by a plurality of the paths. The present technology can be applied to in-car cameras.
Signal generation apparatus
To provide a signal generation apparatus that is used in a ToF camera system especially adopting an indirect system and can suppress occurrence of erroneous distance measurement caused by distance measurement of a same target by a plurality of cameras with a simple configuration. There is provided a signal generation apparatus including a first pulse generator configured to generate a pulse to be supplied to a light source that irradiates light upon a distance measurement target, a second pulse generator configured to generate a pulse to be supplied to a pixel that receives the light reflected by the distance measurement target, and a signal generation section configured to generate a pseudo-random signal for inverting a phase of signals to be generated by the first pulse generator and the second pulse generator.
Photoelectric conversion device
A photoelectric conversion device including a plurality of substrates in a stacked state, the plurality of substrates including a first substrate and a second substrate electrically connected to each other, the photoelectric conversion device comprising: a memory cell unit including row-selection lines that are to be driven upon selection of a row of a memory cell array and column-selection lines that are to be driven upon selection of a column of the memory cell array; and a memory peripheral circuit unit that includes row-selection line connection portions and column-selection line connection portions so as to drive the row-selection lines and to drive the column-selection lines, wherein a first portion that is at least a part of the memory peripheral circuit unit is formed on the first substrate and the memory cell unit is formed on the second substrate.