In an image sensor, an analog-to-digital conversion circuitry generates image data by sequentially performing analog-to-digital conversion processing twice or more on a pixel signal transferred from the pixel array in an operation period of one horizontal cycle, and an image signal processing circuitry receives the image data and performs digital processing on the image data. A timing controller controls the image signal processing circuitry to hold the digital processing during a plurality of holding periods that respectively correspond to portions of two or more ADC processing periods.

An image sensor includes an analog-to-digital conversion circuit that receives pixel signals from column lines, respectively, and converts the pixel signals into first pixel values, respectively. Data buffer clusters correspond to enable signals transferred from a timing controller, respectively, and output second pixel values. Each of the data buffer clusters stores first pixel values, which correspond to some column lines consecutively arranged among the column lines, among the first pixel values and output stored pixel values as some second pixel values among the second pixel values in response to a corresponding enable signal. A digital processing circuit performs digital processing on the second pixel values output from the data buffer clusters.

A photoelectric conversion device comprising a first substrate in which a photoelectric conversion portion is arranged and a second substrate stacked on the first substrate is provided. The second substrate comprises a surface on which a circuit block and a functional cell connected to the block are arranged. Wiring layers including a first layer and a second layer arranged between the first layer and the first substrate are arranged between the first substrate and the surface. The first layer includes first power lines extending in a first direction and arranged in a predetermined period in a second direction, and the second layer includes second power lines arranged in a predetermined period. The functional cell is arranged between two power lines of the first power supply lines, and arranged to fit in a region of any one of the second power lines.

According to an embodiment, an image sensor using photon counting includes: a plurality of sub-pixels arranged in one pixel; pulse generators which are respectively connected to the plurality of sub-pixels, and are configured to generate pulse signals based on electric signals generated based on photons incident on the plurality of sub-pixels; a synchronizer and serializer configured to synchronize and serialize pulse signals respectively output from the pulse generators; and a counter configured to count and output a number of the pulse signals that are synchronized and serialized.

The present disclosure relates to a signal processing apparatus and method, an imaging element, and an electronic apparatus capable of suppressing deterioration of subjective image quality. Driving of a shift register controlling transfer of pixel data of digital data obtained by A/D conversion is stopped in a part or the entirety of a period in which the A/D conversion is performed on a pixel output of an analog signal. The present disclosure can be applied to, for example, a signal processing apparatus, an imaging element, an imaging device, an image processing apparatus, an electronic apparatus, a signal processing method, a program, or the like.

A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.

A solid-state imaging device comprises a first pixel group includes a first photoelectric conversion unit that converts into electric charges reflection light pulses from an object irradiated with an irradiation light pulse, a first electric charge accumulation unit accumulating the electric charges in synchrony with turning on the irradiation light pulses, and a first reset unit resetting the electric charges; and a second pixel group includes a second photoelectric conversion unit that converts the reflection light into electric charges, a second electric charge accumulation unit that accumulates the electric charges synchronously with a switching the irradiation light pulses from on to off, and a second reset unit that releases a reset of the electric charges converted by the second photoelectric conversion unit.

An imaging device that reliably images an object flashing at a period closely analogous to an output period of a moving image within a certain period is provided. A first common frame image, which is synthesized from pixel signals produced by photoelectric conversion elements arranged in row selection lines from a second start row selection line to an end row selection line, is extracted from a first frame image synthesized by an image sensor starting at a first start row selection line. As a moving image, a sequence of the first common frame images and second frame images synthesized by the image sensor starting at the second start row selection line is produced. Due to the phase difference between an imaging period of the first common frame image and an imaging period of the second frame image, a flashing object is captured in any of the frame images.

An imaging device according to an embodiment of the present disclosure includes a pixel array including a plurality of pixels, a scanning control section that controls scanning of the plurality of pixels, and a readout control section that controls reading of the plurality of pixels. The imaging device further includes a first waveform generation part that generates a plurality of control signals for controlling of at least one of the scanning control section or the readout control section, a second waveform generation part that generates a plurality of reference signals, and a failure detection section that detects a failure of the first waveform generation part or the second waveform generation part on a basis of comparison between the plurality of control signals and the plurality of reference signals.

A driver circuit includes: a first node connected to a first signal line; a first switch transistor provided between a first power supply and a first capacitor; a second switch transistor provided between a second power supply and a second capacitor; a third switch transistor provided between the first capacitor and the first node; and a fourth switch transistor provided between the second capacitor and the first node.