An image sensor includes image sensor cells generating an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes charge pump cells to receive clock signals and to source charge to the first power supply node, a delay line including delay line elements generating clock signals, where a first charge pump cell receives a first clock signal generated by a first delay line element, where a second charge pump cell receives a second clock signal generated by a second delay line element, and where a delay between the first clock signal and the second clock signal is determined by the delay line.

The disclosed photoelectric conversion device includes a photoelectric conversion unit outputting a pulse signal in response to an incident of photon, a signal processing unit that is connected to the photoelectric conversion unit and counts the pulse signal, and a control unit that controls the signal processing unit. The signal processing unit includes a first count processing unit and a second count processing unit arranged in parallel. The control unit is configured to set an active period and an inactive period for each of the first count processing unit and the second count processing unit. A period during which the first count processing unit is active includes a first period during which the second count processing unit is active and a second period during which the second count processing unit is inactive.

An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

An image sensing device is provided to comprise: a pixel array of pixels that are operable to sense light to produce pixel signals and are operable to operate in one of a plurality of modes in sensing of light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and configured to output a pixel signal in response to light incident onto the first pixel; and an analog-to-digital converter (ADC) coupled to the pixel array to receive the pixel signal from the first pixel and configured to set, based on the mode selected for the first pixel in generating the pixel signal, an input range indicating a voltage range of the pixel signal and perform an analog to digital conversion of the pixel signal generated by the first pixel to produce pixel data representing the pixel signal based on the input range of the analog-to-digital converter (ADC).

An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.

A semiconductor device includes a first substrate provided with a first circuit unit, and a second substrate provided with a second circuit unit connected to the first circuit unit and a third circuit unit connected to the second circuit unit. The second circuit unit is configured to supply a driving voltage to the first circuit unit, and at least a part of driving voltages of the second circuit unit is configured to be supplied from the first substrate to the second circuit unit.

Disclosed is an image adjustment apparatus including a receiver which is configured to receive a first input image of an object which is time-synchronously captured and a second input image in which a motion event of the object is sensed time-asynchronously, and an adjuster which is configured to adjust the first input image and the second input image.

An imaging device includes an image sensing circuitry configured to receive image signals from pixels, to convert the received image signals into image data, and to output the image data. The imaging device includes a digital processing circuitry configured to process image data in synchronization with a digital clock. The digital processing circuitry includes a digital clock generator configured to generate the digital clock. The digital clock generator is configured to scatter the digital clock, in response to the image sensing circuitry converting the image signals into the image data.

A radiographic imaging apparatus comprising pixels, a drive circuit configured to control the pixels through drive lines and a detection unit configured to detect a start of radiation irradiation is provided. The drive circuit comprises a shift circuit configured to perform a shift operation of changing the drive line to be activated, among the drive lines, in response to a shift control signal input to the drive circuit. The drive circuit has a mode of activating a second drive line among the drive lines in response to the shift control signal input for a second time after a first drive line among the drive lines is activated during a period up to when the detection unit detects the start of radiation irradiation, at least two drive lines of the drive lines being disposed between the first drive line and the second drive line.

Provided is a logic circuit including a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop. The first circuit receives a clock signal and a first reset signal. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. The second circuit receives the clock signal and a signal based on the second reset signal.