Various embodiments of a 3D+imaging system include a focal plane array with in-pixel analog storage elements. In embodiments, an analog pixel circuit is disclosed for use with an array of photodetectors for a sub-frame composite imaging system. In embodiments, a composite imaging system is capable of determining per-pixel depth, white point and black point for a sensor and/or a scene that is stationary or in motion. Examples of applications for the 3D+imaging system include advanced imaging for vehicles, as well as for industrial and smart phone imaging. an extended dynamic range imaging technique is used in imaging to reproduce a greater dynamic range of luminosity.

A photoelectric conversion device includes first to fourth pixel columns. Each of the first to fourth pixel columns includes a plurality of pixels arranged in a predetermined direction. Each of the plurality of pixels arranged in the first to fourth pixel columns includes a photoelectric conversion element configured to receive light of a wavelength region and generate a signal charge. Each of the plurality of pixels arranged in the first to fourth pixel columns further includes a circuit configured to convert the signal charge generated by the photoelectric conversion element into a voltage signal. Directions of reading the voltage signals from the first pixel column and the second pixel column are different from directions of reading the voltage signals from the third pixel column and the fourth pixel column.

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

An imaging device includes an imaging unit including a plurality of pixels, respectively including photoelectric converters and charge accumulation nodes that accumulate signal charge. The imaging unit outputs image data based on signals corresponding to the signal charge accumulated in the charge accumulators. The imaging device includes an image processing unit that processes the image data output by the imaging unit. The imaging unit sequentially outputs a plurality of pieces of image data in one frame period by performing readout nondestructively. The image processing unit generates difference image data by determining a difference between two pieces of image data, selects output image data from initial image data and the difference image data, and combines the output image data and normal readout image data included in the plurality of pieces of image data, to generate combination-result image data.

An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.

Provided are an information processing device, an information processing method, and an information processing program capable of reducing a processing load of convolution processing in a convolutional neural network (CNN). An information processing device (1) according to the present disclosure includes a setting unit (51) and a control unit (52). The setting unit (51) sets exposure time of each of imaging pixels in an imaging unit (2), which includes a plurality of imaging pixels arrayed two-dimensionally, to exposure time corresponding to a convolution coefficient of a first layer of a CNN. The control unit (52) causes transfer of signal charges from imaging pixels, which have been exposed, to a floating diffusion (FD), thereby performing convolution processing.

The photoelectric conversion device includes pixels each including photoelectric converters and a floating diffusion to which charges of the photoelectric converters are transferred, a vertical scanning unit for performing readout processing and reset processing on the pixels while switching the photoelectric converter to be processed and the floating diffusion to be processed, and a control unit that controls the vertical scanning unit. The control unit includes a readout row address generation unit and a reset row address generation unit that generate a row address to be processed. A first cycle in which the photoelectric converter is switched is shorter than a second cycle in which the floating diffusion is switched, an update cycle of the row address is equal to the second cycle, and a setting unit of an update timing of the row address is equal to the length of one cycle of the first cycle.

An image sensor with improved image quality is provided. An image sensor includes a pixel array including a plurality of unit pixels. Each of the unit pixels includes a first photoelectric converter configured to convert received light into charges, a first transfer transistor electrically connected between the first photoelectric converter and a first node, a connection transistor disposed connected to a second node and the first node, a dual conversion transistor electrically connected between a third node and the second node, a second transfer transistor electrically connected between a fourth node and the third node, a second photoelectric converter electrically connected to the fourth node and configured to convert the received light into charges, a first switch electrically connected to the second photoelectric converter and the fourth node, a first capacitor electrically connected to the fourth node, and a electrically second capacitor connected to the third node.

In an imaging apparatus, each of a plurality of pixels has a first semiconductor area having a first conductivity type, a floating diffusion area, and a transfer gate positioned between the first semiconductor area and the floating diffusion area. In a part of the plurality of pixels, a partial area of the first semiconductor area receives a potential supplied from a contact. The part of the plurality of pixels further has a second semiconductor area having a second conductivity type positioned between the partial area and the transfer gate in a planar view.

An image pickup device which suppresses an increase in chip area of peripheral circuits without degrading the performance of a pixel section and makes it possible to prevent costs from being increased. The image pickup device includes a first semiconductor substrate and a second semiconductor substrate. A pixel section includes photo diodes each for generate electric charges by photoelectric conversion, floating diffusions each for temporarily storing the electric charges generated by the photo diode, and amplifiers each connected to the floating diffusion, for outputting a signal dependent on a potential of the associated floating diffusion. Column circuits are connected to vertical signal lines, respectively, for performing predetermined processing on signals output from the pixel section to vertical signal lines.