An Infra Red detector system and method is disclosed that implements a digital coordinate generator onto a 2D focal plane array infrared detector. The method used in this form of the invention by the IR detector system, generates X-Y coordinate data for pixels containing detected target data. Advantageously, it reduces subsequent signal post processing required to generate the same data using numerical processing techniques in software and the latency that this introduces.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

In some embodiments, an imaging device includes a pixel array. At least one of the pixels includes a photodiode that can generate charges, and a select transistor that receives the charges in its bulk. When the select transistor is selected, a pixel current through it may depend on a number of the received charges, thus evidencing how much light it detected. A reset transistor may reset the voltage of the bulk.

An optical electronic device may include a plurality of different optical sources, and a global shutter sensor including an array of global shutter pixels, with each global shutter pixel including a plurality of storage elements. A controller may be coupled to the plurality of optical sources and the global shutter sensor and configured to cause a first optical source to illuminate and a first storage element in each global shutter pixel to store optical data during a first integration period, cause a second optical source to illuminate and a second storage element in each global shutter pixel to store optical data during a second integration period, and output the stored optical data from the first and second storage elements of the global shutter pixels after the first and second integration periods.

In an image capturing apparatus that comprises a pixel area of pixels arranged in a matrix, output circuits apply preset processing to signals read out in parallel from divided areas obtained by dividing the pixel area in a column direction and output the processed signals, a controller performs control to execute first driving for reading out signals corresponding to a predetermined voltage to the output circuits, and second driving for reading out image signals from the pixel area, and a correction circuit generates gain data based on the predetermined voltage for correcting differences between the signals for correction of different columns output for each of the divide areas, and corrects the image signals of the divided areas using the gain data generated for the corresponding divided areas.

An image capturing apparatus comprises a pixel area having a plurality of pixels arranged in a matrix; output circuits that apply preset processing to signals read out in parallel from divided areas obtained by dividing the pixel area in a column direction and output the processed signals in parallel; a controller that performs control to execute first driving for reading out signals for obtaining correction data from the divided areas to the output circuits, and second driving for reading out image signals from the divided areas to the output circuits; and a correction circuit that obtains the correction data from the signals read out through the first driving and corrects the image signals using the correction data. The controller executes the first driving with respect to pixels in a part of rows that includes a row at a border of the divided areas.

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.

An image sensor having photosites forming an array (K×L) of K rows and L columns, including a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n′ photosites, said photosites belonging to n adjacent columns and to n′ adjacent rows, and a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m′ photosites, said photosites belonging to m adjacent columns and to m′ adjacent rows, n adjacent columns of a first set of columns of the array being connected to n×n′ integrator circuits of the first set, m adjacent columns of a second set of columns of the array being connected to m×m′ integrator circuits of the second set, n columns of the first set alternating with m columns of the second set to form the array of photosites.

Ones of row addresses and column addresses of pixels in a first group are the same as those of a second group. A range of the others of the row addresses and the column addresses of the first group excludes that of the second group. A range of the others of row addresses and column addresses is included in a range of the others of the row addresses and the column addresses of the first and second groups. A portion of the range of the row addresses and the column addresses of the first group overlaps with that of the third group, and the other portion of the range of the first group does not overlap with that of the third group. Intra-group addition signals of the first, second, and third groups are obtained.