A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.

A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.

An image capturing apparatus comprises an image sensor including a plurality of pixels and at least one processor or circuit configured to function as: a readout unit that, to carry out a live view display, reads out pixel signals from the image sensor in a first readout mode, and to obtain a still image during the live view display, reads out pixel signals from the image sensor in a second readout mode that is different from the first readout mode; and a control unit that controls the readout unit so that a readout time in the first readout mode is equal to a readout time in the second readout mode.

An electronic device includes a first driver suitable for driving an output node with a first voltage based on an activation control signal for a first driving period, a second driver suitable for driving the output node with a second voltage based on a deactivation control signal for a second driving period, a first booster suitable for boosting voltage of the output node based on an output boost signal for a first boost period, a third driver suitable for driving a control node with a second blocking control signal based on a first blocking control signal for a third driving period, and a blocker suitable for selectively blocking between the first driver and the output node based on a control voltage applied to the control node.

An electronic device includes a driving circuit suitable for driving an output node with an input voltage signal based on a control voltage applied to a control node, a boost circuit suitable for boosting voltage of the output node based on an output boost signal, and a compensating circuit suitable for applying the control voltage to the control node based on control signals to compensate for voltage drop caused by the driving circuit.

A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

A row driver assembly includes a row driver unit. The row driver unit includes a buffer circuit that drives a control signal to a pixel circuit. The buffer circuit is electrically connected to a high buffer supply voltage and to a low buffer supply voltage. A voltage converter circuit supplies the low buffer supply voltage to the buffer circuit. An error detection circuit outputs an active error signal when the low buffer supply voltage is outside a target voltage window.