A row driver assembly includes a row driver unit. The row driver unit includes a buffer circuit that drives a control signal to a pixel circuit. The buffer circuit is electrically connected to a high buffer supply voltage and to a low buffer supply voltage. A voltage converter circuit supplies the low buffer supply voltage to the buffer circuit. An error detection circuit outputs an active error signal when the low buffer supply voltage is outside a target voltage window.

An optical sensor including: a semiconductor layer including a source region and a drain region; a gate electrode facing a region between the source region and the drain region; a photoelectric conversion layer between the region and the gate electrode; and a first transistor having a first gate coupled to one of the source region and the drain region.

In an imaging device, a differential stage includes an input transistor having an input node connected to a floating diffusion portion, a first control line and a second control line are located in a plurality of sets, the first control line is connected to connection portions of some sets of the plurality of sets, and the second control line is connected to connection portions of the other sets of the plurality of sets.

An optical sensor includes: a semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing to the semiconductor layer; a gate insulating layer between the third region and the gate electrode, the gate insulating layer including a photoelectric conversion layer; a signal detection circuit including a first signal detection transistor, a first input of the first signal detection transistor being electrically connected to the first region; a first transfer transistor connected between the first region and the first input; and a first capacitor having one end electrically connected to the first input. The signal detection circuit detects an electrical signal corresponding to a change of a dielectric constant of the photoelectric conversion layer, the change being caused by incident light.

Techniques for detecting pulsed radiation. A CMOS sensor array being irradiated across at least a portion of the array with pulsed radiation is addressed using a rolling shutter operation. The sensor array is read to extract the integrated energy from each sensor element and convert the integrated energy into a pixel value for a pixel in a radiation image. A pulse detection operation is then applied to the radiation image to obtain a pulse repetition frequency of the pulsed radiation. The pulse detection operation includes extracting a beat signal, calculating a beat frequency and peak to trough ratio from the beat signal, and determining the pulse repetition frequency therefrom. Particularly suited to the technical field of pulsed laser detection. Also relates to a pulse detector for the same.

Techniques for detecting pulsed radiation. A CMOS sensor array being irradiated across at least a portion of the array with pulsed radiation is addressed using a rolling shutter operation. The sensor array is read to extract the integrated energy from each sensor element and convert the integrated energy into a pixel value for a pixel in a radiation image. A pulse detection operation is then applied to the radiation image to obtain a pulse repetition frequency of the pulsed radiation. The pulse detection operation includes extracting a beat signal, calculating a beat frequency and peak to trough ratio from the beat signal, and determining the pulse repetition frequency therefrom. Particularly suited to the technical field of pulsed laser detection. Also relates to a pulse detector for the same.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

An image sensor may be formed from stacked first and second substrates. An array of imaging pixels that each have a photodiode and accompanying transistors may be formed in the first substrate. Verification circuitry may also be formed in the first substrate. Row control circuitry may be formed in the second substrate. The row control circuitry may provide row control signals to the array of imaging pixels. The verification circuitry may also receive the row control signals from the row control circuitry. The first substrate may include a plurality of n-channel metal-oxide semiconductor transistors and may not include any p-channel metal-oxide semiconductor transistors. The second substrate may also include a p-channel metal-oxide semiconductor current source coupled to the verification circuitry. Only the verification circuitry portions that are enabled by control signals from the row control circuitry may receive current from the current source.

An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.