The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

A pixel portion includes a first pixel array in which a plurality of photoelectric conversion reading parts of first pixels are arranged in a matrix, a holding part array in which a plurality of signal holding parts of first pixels are arranged in a matrix, and a second pixel array in which a plurality of photoelectric conversion reading parts of second pixels are arranged in a matrix, wherein, at the time of a rolling shutter mode, readout signals of the photoelectric conversion reading parts of the first pixels and the second pixels are immediately output to a first vertical signal line without following a bypass route and, at the time of a global shutter mode, held signals of the signal holding parts of the first pixels are output to a second vertical signal line. Due to this, a solid-state imaging device can prevent complication of the configuration.

The present disclosure relates to a solid-state imaging device, an image pickup apparatus, and an electronic device capable of stably supplying high-speed control signals and clock signals. In the area AD method in which analog-digital conversion of a pixel signal is performed for each ADC area corresponding to a pixel group including a plurality of pixels, a repeater element is regularly arranged in each area group unit including one or more ADC areas, to re-drive control signals for controlling a plurality of the ADC areas. The present disclosure is applicable to a solid-state imaging device.

A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.

An endoscope includes a cable in which a first clock signal wire and a second clock signal wire are provided inside and a differential clock signal receiving section for clocks to be supplied to an image pickup device, and a video processor includes a current detector inserted in VCCI/O for the differential clock signal receiving section, a differential signal output section configured to perform conversion into two differential clock signals, respective phases of the two differential clock signals being reverse of each other, and output the two differential clock signals, and an FPGA configured to, based on a current value detected by the current detector, determine a short or an open in the first clock signal wire and the second clock signal wire.

Provided are a comparison device capable of achieving a small area by using one small sampling capacitor for an input terminal and improving linearity by using a fixed reference voltage and a CMOS image sensor using the same. The comparison device may include a comparator configured to compare a pixel signal inputted through a positive input terminal with a ramp signal, a first sampling capacitor configured to be provided between an input terminal of the ramp signal and the positive input terminal of the comparator, a sampling switch configured to be provided between an output terminal of the comparator and a negative input terminal of the comparator, and a second sampling capacitor configured to be provided between a ground terminal and the negative input terminal of the comparator.

A ramp signal generator is provided. The ramp signal generator includes a bias generation circuit, a transferring switch, a sampling capacitor, a current cell circuit, a current to voltage converter and a tuning circuit. The bias generation circuit generates a bias voltage. The transferring switch transfers the bias voltage to a sampling node in response to a first switching control signal. The sampling capacitor samples the bias voltage. The current cell circuit provides a first output node with a first ramping current in response to a sampled bias voltage and switching code pairs. The current to voltage converter includes a first load resistor to convert the first ramping current to a first ramp signal. The tuning circuit includes a capacitor that couples the sampled bias voltage to the first ramp signal, and adjusts a degree of nonlinearity of the first ramp signal in response to a tuning signal.

An image sensor is provided, the image sensor including: an imaging unit that has a first imaging region and a second imaging region, and outputs: a first pixel signal generated according to light incident on the first imaging region; and a second pixel signal generated according to light incident on the second imaging region; a first ramp generating unit that generates a first ramp signal; a second ramp generating unit that generates a second ramp signal; a first signal converting unit that converts the first pixel signal into a first digital image signal based on a result of comparison between the first pixel signal and the first ramp signal; and a second signal converting unit that converts the second pixel signal into a second digital image signal based on a result of comparison between the second pixel signal and the second ramp signal.

An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.