An imaging device according to the present disclosure includes: a clock signal generator; a plurality of light-receiving pixels; a plurality of gate circuits; and a plurality of counters. The clock signal generator supplies a first clock signal to a clock signal path. The plurality of light-receiving pixels is provided side by side in the first direction and grouped into a plurality of pixel groups in the first direction. The plurality of light-receiving pixels each includes a light-receiving circuit, a comparison circuit, and a latch circuit. The comparison circuit performs a comparison operation on the basis of a pixel signal and a reference signal having a ramp waveform. The latch circuit latches a time code on the basis of a result of comparison. The plurality of gate circuits is each configured to output a signal in a clock signal path as a second clock signal. The plurality of gate circuits each controls, on the basis of a control signal, whether or not to output the second clock signal. The plurality of counters each generates the time code on the basis of the second clock signal supplied from the corresponding gate circuit and supplies the generated time code to two or more light-receiving pixels belonging to the corresponding pixel group.

An imaging device according to the present disclosure includes a light-receiving pixel; a reference signal generator; a first amplification section; a second amplification section; a third amplification section; and a counter. The first amplification section is coupled to a first power supply node and a second power supply node. The first amplification section performs a comparison operation on the basis of a pixel signal and a reference signal. The first amplification section outputs a signal corresponding to a result of the comparison to a first node. The second amplification section includes a first transistor and a first load circuit. The first transistor includes a gate coupled to the first node, a drain coupled to a second node, and a source coupled to the second power supply node. The third amplification section includes a second transistor and a first switch. The second transistor includes a gate coupled to the second node, a source coupled to the first power supply node, and a drain coupled to a third node. The first switch applies a predetermined voltage to the third node by being turned on. The counter is coupled to a third power supply node and a fourth power supply node. The counter stops a count operation on the basis of a voltage of the third node.

An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

There is provided an imaging device capable of suppressing an occurrence of shading in any input image at any shutter timing when the fine shutter is implemented without restriction on the exposure time.

The imaging device includes a shutter function capable of performing a shutter operation at a desired timing within one horizontal synchronization period, in which in a pixel layout configuration in which pixels each including a photoelectric conversion unit are disposed in a matrix shape, a pixel control line is wired for each pixel row with respect to a matrix-like pixel array, and a vertical signal line and a power supply line of a high-potential-side power supply voltage are wired for each pixel column in a wiring layer different from a wiring layer in which the pixel control line is wired, the vertical signal line is shielded by a shielding power supply line of a low-potential-side power supply voltage.

A driver chip is provided. The driver chip includes a light-emitting module and a wafer substrate. The light-emitting module has multiple pins. The wafer substrate has a first surface and a second surface. The wafer substrate includes a photodiode, an image sensing circuit, and a light-emitting driving circuit. The photodiode is disposed on the second surface of the wafer substrate. The image sensing circuit is disposed in the wafer substrate and is electrically connected to the photodiode to drive the photodiode. The light-emitting driving circuit is disposed in the wafer substrate, and is electrically connected to the multiple pins of the light-emitting module via multiple connection units on the first surface of the wafer substrate to drive the light-emitting module.

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

Disclosed are a chip with automatic clock signal correction and an automatic correction method. The chip includes a transmission interface, an oscillator and a correction logic circuit. The transmission interface provides a first clock signal. The oscillator generates a second clock signal. The correction logic circuit is coupled to the oscillator and the transmission interface, and performs correction operation to count the first clock signal to generate a first clock count value, and count the second clock signal to generate a second clock count value. When the first clock count value is equal to the first count target value, the correction logic circuit stops counting, and calculates a correction value based on the second clock count value and the second count target value. The correction logic circuit outputs the correction value to the oscillator, and the oscillator corrects a frequency of the second clock signal according to the correction value.

An image sensor and an image sensing method are provided. The image sensor includes a first pixel circuit, a second pixel circuit, a ramp signal generating circuit, a comparator, and a signal processing circuit. The first pixel circuit has a first floating diffusion node. The second pixel circuit has a second floating diffusion node. The ramp signal generating circuit respectively provides a first ramp signal and a second ramp signal to the first floating diffusion node and the second floating diffusion node during a dark sun detection period. The comparator receives a first node voltage of the first floating diffusion node and a second node voltage of the second floating diffusion node. The signal processing circuit determines whether to output an output signal and determines whether to overwrite a digital value corresponding to a sensing signal according to whether the comparator is triggered.

An image sensor and an operation method thereof are provided. The image sensor includes a first pixel circuit and a ramp signal generator. The first pixel circuit includes a first pixel unit; a first transfer transistor coupled to the first pixel unit and a first floating diffusion node; a first readout transistor coupled to the first floating diffusion node; a first ramp capacitor coupled to the first floating diffusion node and receiving a first ramp signal; and a first reset transistor coupled to the first floating diffusion node and receiving a reset signal. The ramp signal generator is coupled to the first ramp capacitor and configured to provide the first ramp signal. A voltage range or a counting result of the pixel circuit during at least one of a reset period and a readout period has an offset.

Disclosed are an image sensor and an image sensing method. The image sensor includes a first pixel circuit. The first pixel circuit includes a first driving transistor, a first selection transistor, a first transfer transistor, a first reset transistor and a first sensing unit. A control terminal of the first selection transistor is used for receiving a first selection signal. A control terminal of the first transmitting transistor is used for receiving a first transmitting signal. The image sensing method includes the following steps: receiving a first reset signal during a reset period through a control terminal of the first reset transistor; and receiving a first ramp signal during a sensing period through a control terminal of the first reset transistor.