Provided is an image sensor including a pixel array that includes a plurality of pixels, wherein each of the plurality of pixels is configured to generate an analog signal in response to incident light; an analog-to-digital converter that includes a counter, wherein the analog-to-digital converter is configured to convert the analog signal into a digital signal; and a test circuit that is configured to change a reset code according to a horizontal time period, wherein the reset code corresponds to a first counting value during a reset time period of a test mode according to a count clock signal, and wherein the test circuit is configured to test a counting operation of the counter based on the reset code that changes according to the horizontal time period.

The present disclosure provides a pixel collection circuit which at least includes a photoelectric detection unit, an optical flow information timing trigger unit, an optical flow information timing control unit, an optical flow information timing unit and a row selection output unit. The present disclosure further provides an optical flow sensor including the pixel collection circuit, and an optical flow and image information collection system.

A solid-state image sensor with quasi-global shutter function and a method of operating the same. A row control unit of the image sensor is configured to determine exceptional pixel rows for which a pre-scheduled global exposure control pulse would fully or partially coincide with a sequentially applied readout control pulse that is selecting a number of pixel rows of the pixel array to be read out. The pre-scheduled global exposure control pulse is applied simultaneously to all but the exceptional pixel rows and delayed and/or advanced versions of the exposure control pulse are applied to the exceptional pixel rows.

An image sensor according to some example embodiments of the present inventive concepts may operate in a global shutter mode, and each pixel circuit may support a high conversion gain (HCG) mode and a low conversion gain (LCG) mode so as to have high dynamic range (HDR). Accordingly, the image sensor according to some example embodiments of the present inventive concepts may have HDR and may generate a high-quality image.

The present disclosure provides a pixel collection circuit and an image sensor. The image collection circuit includes: a movement detection module configured to detect a change in a light intensity in a field of view, and generate a pixel triggering signal when the change in the light intensity exceeds a predetermined threshold so as to indicate the pixel collection circuit to be in a triggered state; and a time signal generation module coupled to the movement detection module and configured to generate a time signal upon the receipt of the pixel triggering signal, the time signal being used to represent time information about a time point at which the pixel collection circuit is triggered. The movement detection module and the time signal generation module are coupled to a reading unit, so that the reading unit scans the pixel collection circuit to output the time information about the pixel collection circuit.

A pixel circuit 200 includes a readable pixel 210, a comparator 220, and a selector counter circuit 230. The readable pixel 210 performs photoelectric conversion at a photodiode PD11 and produces a readable signal corresponding to an illuminance condition of incident light. The readable pixel 210 includes an overflow path extending to a floating diffusion FD11. The comparator 220 compares a voltage signal (SFout) read out from the readable pixel 210 against a reference signal Vref and outputs a comparison result signal Vout indicating the result of the comparison. The selector counter circuit 230 includes a selector circuit for selecting an external clock or the output Vout from the comparator and a counter circuit for counting the output from the selector circuit.

An imaging device having a digital circuit block therein subjected to in-frame DVFS during a frame sequence of the sensing operating mode. In an example embodiment, the in-frame DVFS causes a higher power-supply voltage and a higher clock frequency to be supplied to the digital circuit block during read periods of the frame sequence, and a lower power-supply voltage and a lower clock frequency to be supplied to the digital circuit block during V-blanking periods of the frame sequence. The lower power-supply voltage and clock frequency are selected to be sufficient for the digital circuit block to support the pertinent functions thereof during the V-blanking periods without adversely impacting performance. For example, the lower power-supply voltage is sufficient for a SRAM of the digital circuit block to retain data therein. Beneficially, the in-frame DVFS enables the imaging device to perform motion detection while consuming very little power.

An image sensing device includes a pixel region provided in a first portion of a semiconductor substrate such that photoelectric conversion elements for converting incident light into an electrical signal are disposed in the first portion of the semiconductor substrate, a dummy region located outside the pixel region to surround the pixel region and provided in a second portion of the semiconductor substrate without including a photoelectric conversion element, first microlenses disposed over the first portion of the semiconductor substrate and in the pixel region, the first microlenses configured to converge the incident light onto corresponding photoelectric conversion elements, second microlenses disposed over the second portion of the semiconductor substrate and in the dummy region, the second microlenses isolated from the first microlenses, and at least one alignment pattern disposed in the second portion of semiconductor substrate so as to be aligned with the second microlenses.

An image sensing device includes a plurality of first pixel blocks, each including a plurality of first imaging pixels configured to share one first color filter; a plurality of second pixel blocks, each including a plurality of second imaging pixels configured to share one second color filter having a second color filter; a plurality of third pixel blocks, each including a plurality of third imaging pixels configured to share one third color filter; an upper grid structure disposed in one or more boundary regions between the first to third pixel blocks within a region disposed in the first to third color filters; and a lower grid structure disposed between a substrate layer and each of the first to third color filters, at least a portion of to the lower grid structure vertically overlapping a boundary region of corresponding imaging pixels in each of the first to third pixel blocks.

An imaging apparatus includes an imaging unit, a storage unit, an image processing unit, an image signal output unit, and a timing control unit. The timing control unit generates a first vertical synchronizing signal for driving the imaging unit and supplies the first vertical synchronizing signal to the imaging unit, and generates a second vertical synchronizing signal which is obtained by delaying the first vertical synchronizing signal at least by a predetermined time which is variable according to contents of the image processing performed and supplies the second vertical synchronizing signal to the display unit. The timing control unit controls the image signal output unit so that the image signal is read from the storage unit by being delayed by a phase difference between the first vertical synchronizing signal and the second vertical synchronizing signal, after outputting of the imaging signal from the imaging unit.