Solid-state imaging devices are disclosed. In one example, a solid-state imaging device includes a conversion circuit connected to a vertical signal line of a pixel array, a voltage generation circuit that outputs a predetermined voltage, and a reference voltage generation circuit that receives the predetermined voltage and outputs a reference voltage. The reference voltage generation circuit includes an operational amplifier that amplifies the predetermined voltage and outputs the reference voltage, a capacitive element having one end connected to an input of the operational amplifier that is different from an input that receives the predetermined voltage, a first switching circuit that connects the other end of the capacitive element to either the predetermined voltage output from the voltage generation circuit or a feedback loop of the operational amplifier, and a second switching circuit that selectively connects the one end of the capacitive element to the feedback loop of the operational amplifier.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

The device comprises an array (8) of cells (10), with each cell having a single-photon avalanche diode (12) and a quenching circuit (14). Each cell (10) further comprises a first analog output (A) as well as a digital output (D). A latch (20) is provided for buffering a pulse generated by the diode (12) and selectively feeding it to the digital output (D). The cells (10) are arranged in rows and columns, and the outputs (A, D) are fed to analog and digital bus lines (40, 42) for off-array analog and digital signal processing. A data switch (54) and a shift register (58) are provided for serializing various measurement results detected by the device.

The device comprises an array (8) of cells (10), with each cell having a single-photon avalanche diode (12) and a quenching circuit (14). Each cell (10) further comprises a first analog output (A) as well as a digital output (D). A latch (20) is provided for buffering a pulse generated by the diode (12) and selectively feeding it to the digital output (D). The cells (10) are arranged in rows and columns, and the outputs (A, D) are fed to analog and digital bus lines (40, 42) for off-array analog and digital signal processing. A data switch (54) and a shift register (58) are provided for serializing various measurement results detected by the device.

The present invention relates to a delta image sensor comprising an arrangement of pixels and a plurality of acquisition circuits corresponding to at least one pixel and formed as part of an integrated circuit. Each acquisition circuit includes at least one sensor circuit comprising a photosensor configured to generate a sensor signal, VSIG, depending on a light signal illuminating the photosensor of the at least one pixel; at least one analogue to digital conversion, A/D, circuit configured to convert a current VSIG to a digital signal; at least one digital storage circuit configured to store a representation of at least one digital signal corresponding to a previous VSIG; at least one digital comparison circuit configured to compare the level of the stored representation with the current VSIG to detect whether a changed level is present; and at least one digital output circuit configured to generate an event output under the condition of the changed level. The sensor circuit is configured to change an analogue function of its read-out characteristics to generate a respective changed VSIG.

The present invention relates to a delta image sensor comprising an arrangement of pixels and a plurality of acquisition circuits corresponding to at least one pixel and formed as part of an integrated circuit. Each acquisition circuit includes at least one sensor circuit comprising a photosensor configured to generate a sensor signal, VSIG, depending on a light signal illuminating the photosensor of the at least one pixel; at least one analogue to digital conversion, A/D, circuit configured to convert a current VSIG to a digital signal; at least one digital storage circuit configured to store a representation of at least one digital signal corresponding to a previous VSIG; at least one digital comparison circuit configured to compare the level of the stored representation with the current VSIG to detect whether a changed level is present; and at least one digital output circuit configured to generate an event output under the condition of the changed level. The sensor circuit is configured to change an analogue function of its read-out characteristics to generate a respective changed VSIG.

An imaging apparatus includes an imaging element including photodiode divided pixels, and a control unit. The control unit performs control to execute first readout in which an addition value of a first pixel and a second pixel constituting a photodiode divided pixel is read out as a pixel value constituting an image and second readout of performing readout in which a value of the first pixel and a value of the second pixel used for phase difference detection can be obtained from a photodiode divided pixel that is not a readout target in the first readout. In this case, the first readout is performed after performing the second readout in one vertical period.

An imaging apparatus includes an imaging element including photodiode divided pixels, and a control unit. The control unit performs control to execute first readout in which an addition value of a first pixel and a second pixel constituting a photodiode divided pixel is read out as a pixel value constituting an image and second readout of performing readout in which a value of the first pixel and a value of the second pixel used for phase difference detection can be obtained from a photodiode divided pixel that is not a readout target in the first readout. In this case, the first readout is performed after performing the second readout in one vertical period.

The present technology relates to an imaging element and an electronic device capable of preventing light from leaking into an adjacent pixel. A semiconductor layer in which a first pixel in which a read pixel signal is used to generate an image, and a second pixel in which the read pixel signal is not used to generate an image are arranged, and a wiring layer stacked on the semiconductor layer are provided, and a structure of the first pixel and a structure of the second pixel are different. A first inter-pixel separation portion that separates the semiconductor layer of the adjacent first pixels, and a second inter-pixel separation portion that separates the semiconductor layer of the adjacent second pixels are further provided, and the first inter-pixel separation portion and the second inter-pixel separation portion are provided with different structures. The present technology can be applied to an imaging element in which dummy pixels are arranged.

The present disclosure relates to a method and system for imaging a scene. The method includes generating a shutter pattern and applying the shutter pattern to a photodetector array. The system includes a sensor architecture in three dimensions, where elements of the sensor architecture are stacked in two or more layers. Some elements of the sensor architecture include a photodetector array, register array, a generator to generate shutter patterns, readout circuitry, and an ISP.