An imaging device includes pixel sensors. A drive-sense circuit is configured to generating a sensed signal corresponding to one of pixel sensors. The drive-sense circuit includes: a first conversion circuit configured to convert, a receive signal component of a sensor signal corresponding to the one of the pixel sensors into the sensed signal, wherein the sensed signal indicates a change in a capacitance associated with the one of the pixel sensors; a second conversion circuit configured to generate, based on the sensed signal, a drive signal component of the sensor signal corresponding to the one of the pixel sensors. The drive-sense circuit is further configured to generate other sensed signals corresponding to other ones of the pixel sensors for the other ones of the pixel sensors. A graphics processing module is configured to generate image data based on the sensed signal and the other sensed signals.

This disclosure presents a novel smart complementary metal oxide semiconductor (CMOS) sensor that can detect the “bright” pixels and export the light intensity and location of the selected pixels only. The detecting function is achieved by applying a thresholding criteria method. A novel CMOS architecture is proposed. The FPA-implemented COMS is shared by two sets of column processing circuitry for selecting, processing and exporting the data from top half and bottom half of FPA respectively. The CMOS architecture comprises a re-routing scheme, multiple I/Os deployment, parallel-shifting FIFO memory buffers, and interleaved timing scheme.

An imaging device includes a pixel array including a 4x4 grouping of pixel circuits. The 4x4 grouping of pixel circuits includes four rows and four columns of the pixel array. A plurality of bitlines includes a first bitline, a second bitline, a third bitline, and a fourth bitline. Each one of the first, second, third, and fourth bitlines is coupled to a respective four pixel circuits in the 4x4 grouping of pixel circuits. Each one of the first, second, third, and fourth bitlines is coupled to all four of the rows and to all four of the columns of the 4x4 grouping of pixel circuits.

An image capturing apparatus comprising: a plurality of SPAD pixels arrayed two-dimensionally; and a plurality of signal processing units that are provided so as to correspond, respectively, to the plurality of SPAD pixels, wherein each of the plurality of signal processing units comprises a request unit configured to issue a readout request in accordance with detection of a predetermined numbers of photons by the corresponding SPAD pixel, and an arbitration unit configured to select and output one of one or more readout requests issued by the request unit and another readout request received from another signal processing unit, The image capturing apparatus further comprises a request detection unit configured to detect the readout request output by the arbitration unit, where the request detection unit detects and counts the readout requests issued in a predetermined period.

According to one embodiment, a solid-state imaging device includes a plurality of pixels, a plurality of sampling switches, a plurality of sample-and-hold circuits, and a plurality of output switches. The plurality of pixels are arranged at least in a column direction. The plurality of sampling switches are configured to sample signals outputted from the pixels belonging to columns in parallel. The plurality of sample-and-hold circuits are configured to sample and hold signals outputted from the plurality of sampling switches. The plurality of output switches are configured to output signals stored in the plurality of sample-and-hold circuits at predetermined timing.

A semiconductor photomultiplier module (20; 30; 40) comprises a first semiconductor chip (21; 31; 41) disposed in a first plane and comprising an array (21.1) of single-photon avalanche diodes (SPAD), a second semiconductor chip (22; 32; 42) disposed in a second plane and comprising a first part of an electronic read-out circuit, and a third semiconductor chip (26; 36; 46) comprising a second part of the electronic read-out circuit, wherein the first semiconductor chip (21; 31; 41) and the second semiconductor chip (22; 32; 42) are arranged in a stacked relationship and vertical electrical interconnects (23) are arranged to electrically interconnect the first semiconductor chip (21; 31; 41) with the second semiconductor chip (22; 32; 42).

A semiconductor photomultiplier module (20; 30; 40) comprises a first semiconductor chip (21; 31; 41) disposed in a first plane and comprising an array (21.1) of single-photon avalanche diodes (SPAD), a second semiconductor chip (22; 32; 42) disposed in a second plane and comprising a first part of an electronic read-out circuit, and a third semiconductor chip (26; 36; 46) comprising a second part of the electronic read-out circuit, wherein the first semiconductor chip (21; 31; 41) and the second semiconductor chip (22; 32; 42) are arranged in a stacked relationship and vertical electrical interconnects (23) are arranged to electrically interconnect the first semiconductor chip (21; 31; 41) with the second semiconductor chip (22; 32; 42).

The disclosed photoelectric conversion device includes a pixel including a photoelectric conversion unit, an AD conversion unit that performs an AD conversion on an analog signal generated in the pixel, and a control unit configured to control the AD conversion unit. The control unit is configured to control the AD conversion unit to perform a plurality of times of the AD conversion on the same analog signal. A length of a first AD conversion period of the plurality of times is shorter than a length of a second AD conversion period of the plurality of times. A change rate of the reference signal in the second AD conversion period is smaller than a change rate of the reference signal in the first AD conversion period. In each of the first and second AD conversion periods, a potential of the reference signal changes to a first level.

An image capturing device including a pixel chip having pixel blocks each including one or more pixels; and a signal processing chip having a first control block including a first converting unit for converting a signal from a pixel in at least a first pixel block into a digital signal, and a first storage unit storing the digital signal, and a second control block next to the first control block in a column direction and including a second converting unit for converting a signal from a pixel included in at least a second pixel block into a digital signal, and a second storage unit storing the digital signal, wherein the second converting unit and the second storage unit in the second control block are reversed vertically to the first converting unit and the first storage unit in the first control block.

A solid-state imaging apparatus includes: an imaging section that acquires image data; and a control section that changes time of reading out the image data in accordance with time of DNN processing on the image data.